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yosys/techlibs
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Clifford Wolf 516e8828f2 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
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cmos Improved liberty file test case 2015-07-06 17:45:56 +02:00
common Added "synth -nofsm" 2015-07-02 15:25:38 +02:00
ice40 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
xilinx Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00