mirror of https://github.com/YosysHQ/yosys.git
219 lines
7.5 KiB
C++
219 lines
7.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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static void split_portname_pair(std::string &port1, std::string &port2)
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{
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size_t pos = port1.find_first_of(':');
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if (pos != std::string::npos) {
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port2 = port1.substr(pos+1);
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port1 = port1.substr(0, pos);
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}
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}
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struct IopadmapPass : public Pass {
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IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
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virtual void help()
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{
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log("\n");
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log(" iopadmap [options] [selection]\n");
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log("\n");
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log("Map module inputs/outputs to PAD cells from a library. This pass\n");
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log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
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log("the resulting cells to more sophisticated PAD cells.\n");
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log("\n");
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log(" -inpad <celltype> <portname>[:<portname>]\n");
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log(" Map module input ports to the given cell type with\n");
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log(" the given port name. if a 2nd portname is given, the\n");
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log(" signal is passed through the pad call, using the 2nd\n");
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log(" portname as output.\n");
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log("\n");
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log(" -outpad <celltype> <portname>[:<portname>]\n");
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log(" -inoutpad <celltype> <portname>[:<portname>]\n");
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log(" Similar to -inpad, but for output and inout ports.\n");
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log("\n");
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log(" -widthparam <param_name>\n");
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log(" Use the specified parameter name to set the port width.\n");
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log("\n");
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log(" -nameparam <param_name>\n");
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log(" Use the specified parameter to set the port name.\n");
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log("\n");
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log(" -bits\n");
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log(" create individual bit-wide buffers even for ports that\n");
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log(" are wider. (the default behavio is to create word-wide\n");
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log(" buffers use -widthparam to set the word size on the cell.)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
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std::string inpad_celltype, inpad_portname, inpad_portname2;
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std::string outpad_celltype, outpad_portname, outpad_portname2;
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std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
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std::string widthparam, nameparam;
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bool flag_bits = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-inpad" && argidx+2 < args.size()) {
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inpad_celltype = args[++argidx];
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inpad_portname = args[++argidx];
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split_portname_pair(inpad_portname, inpad_portname2);
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continue;
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}
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if (arg == "-outpad" && argidx+2 < args.size()) {
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outpad_celltype = args[++argidx];
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outpad_portname = args[++argidx];
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split_portname_pair(outpad_portname, outpad_portname2);
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continue;
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}
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if (arg == "-inoutpad" && argidx+2 < args.size()) {
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inoutpad_celltype = args[++argidx];
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inoutpad_portname = args[++argidx];
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split_portname_pair(inoutpad_portname, inoutpad_portname2);
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continue;
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}
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if (arg == "-widthparam" && argidx+1 < args.size()) {
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widthparam = args[++argidx];
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continue;
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}
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if (arg == "-nameparam" && argidx+1 < args.size()) {
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nameparam = args[++argidx];
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continue;
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}
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if (arg == "-bits") {
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flag_bits = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &it : design->modules)
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{
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RTLIL::Module *module = it.second;
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if (!design->selected(module) || module->get_bool_attribute("\\blackbox"))
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continue;
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for (auto &it2 : module->wires)
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{
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RTLIL::Wire *wire = it2.second;
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if (!wire->port_id || !design->selected(module, wire))
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continue;
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std::string celltype, portname, portname2;
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if (wire->port_input && !wire->port_output) {
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if (inpad_celltype.empty()) {
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log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = inpad_celltype;
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portname = inpad_portname;
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portname2 = inpad_portname2;
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} else
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if (!wire->port_input && wire->port_output) {
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if (outpad_celltype.empty()) {
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log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = outpad_celltype;
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portname = outpad_portname;
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portname2 = outpad_portname2;
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} else
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if (wire->port_input && wire->port_output) {
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if (inoutpad_celltype.empty()) {
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log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = inoutpad_celltype;
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portname = inoutpad_portname;
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portname2 = inoutpad_portname2;
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} else
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log_abort();
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if (!flag_bits && wire->width != 1 && widthparam.empty()) {
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log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
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RTLIL::Wire *new_wire = NULL;
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if (!portname2.empty()) {
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new_wire = new RTLIL::Wire;
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*new_wire = *wire;
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wire->name = NEW_ID;
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module->wires[wire->name] = wire;
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module->wires[new_wire->name] = new_wire;
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}
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if (flag_bits)
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{
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for (int i = 0; i < wire->width; i++)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = RTLIL::escape_id(celltype);
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cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
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if (!portname2.empty())
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cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
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if (!widthparam.empty())
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cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
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if (!nameparam.empty())
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cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
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cell->attributes["\\keep"] = RTLIL::Const(1);
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module->add(cell);
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}
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}
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else
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = RTLIL::escape_id(celltype);
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cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
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if (!portname2.empty())
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cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
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if (!widthparam.empty())
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cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
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if (!nameparam.empty())
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cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
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cell->attributes["\\keep"] = RTLIL::Const(1);
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module->add(cell);
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}
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wire->port_id = 0;
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wire->port_input = false;
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wire->port_output = false;
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}
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module->fixup_ports();
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}
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}
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} IopadmapPass;
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