yosys/passes/techmap
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
dfflibmap.cc Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 2014-03-11 14:24:24 +01:00
extract.cc Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
filterlib.cc Moved dfflibmap from passes/dfflibmap to passes/techmap 2013-10-16 15:32:26 +02:00
hilomap.cc Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
iopadmap.cc Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
libparse.cc Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00
libparse.h renamed LibertyParer to LibertyParser 2014-01-14 18:57:47 +01:00
simplemap.cc Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
techmap.cc Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00