yosys/passes
Clifford Wolf 9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
..
cmds Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
equiv Fix equiv_simple, old behavior now available with "equiv_simple -short" 2017-04-28 18:57:53 +02:00
fsm Remove some dead code from fsm_map 2017-08-21 15:02:16 +02:00
hierarchy Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
memory Typo fix. 2016-09-08 10:57:16 +03:00
opt Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
proc Add src attribute to extra cells generated by proc_dlatch 2017-09-09 10:18:08 +02:00
sat Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
techmap Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
tests Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00