mirror of https://github.com/YosysHQ/yosys.git
334 lines
11 KiB
C++
334 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool memrd_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
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{
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return a->name < b->name;
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}
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bool memwr_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
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{
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return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
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}
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struct OptMemFeedbackWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap, sigmap_xmux;
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std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;
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std::map<pair<std::set<std::map<SigBit, bool>>, SigBit>, SigBit> conditions_logic_cache;
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// -----------------------------------------------------------------
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// Converting feedbacks to async read ports to proper enable signals
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// -----------------------------------------------------------------
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bool find_data_feedback(const std::set<RTLIL::SigBit> &async_rd_bits, RTLIL::SigBit sig,
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std::map<RTLIL::SigBit, bool> &state, std::set<std::map<RTLIL::SigBit, bool>> &conditions)
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{
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if (async_rd_bits.count(sig)) {
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conditions.insert(state);
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return true;
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}
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if (sig_to_mux.count(sig) == 0)
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return false;
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RTLIL::Cell *cell = sig_to_mux.at(sig).first;
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int bit_idx = sig_to_mux.at(sig).second;
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std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
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std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
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std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
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std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
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log_assert(sig_y.at(bit_idx) == sig);
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for (int i = 0; i < int(sig_s.size()); i++)
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if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
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if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
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RTLIL::SigSpec new_b = cell->getPort(ID::B);
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new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
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cell->setPort(ID::B, new_b);
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}
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return false;
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}
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for (int i = 0; i < int(sig_s.size()); i++)
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{
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if (state.count(sig_s[i]) && state.at(sig_s[i]) == false)
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continue;
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std::map<RTLIL::SigBit, bool> new_state = state;
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new_state[sig_s[i]] = true;
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if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
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RTLIL::SigSpec new_b = cell->getPort(ID::B);
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new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
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cell->setPort(ID::B, new_b);
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}
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}
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std::map<RTLIL::SigBit, bool> new_state = state;
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for (int i = 0; i < int(sig_s.size()); i++)
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new_state[sig_s[i]] = false;
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if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
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RTLIL::SigSpec new_a = cell->getPort(ID::A);
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new_a.replace(bit_idx, RTLIL::State::Sx);
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cell->setPort(ID::A, new_a);
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}
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return false;
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}
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RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, SigBit olden, int &created_conditions)
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{
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auto key = make_pair(conditions, olden);
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if (conditions_logic_cache.count(key))
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return conditions_logic_cache.at(key);
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RTLIL::SigSpec terms;
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for (auto &cond : conditions) {
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RTLIL::SigSpec sig1, sig2;
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for (auto &it : cond) {
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sig1.append(it.first);
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sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
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}
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terms.append(module->Ne(NEW_ID, sig1, sig2));
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created_conditions++;
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}
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if (olden.wire != nullptr || olden != State::S1)
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terms.append(olden);
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if (GetSize(terms) == 0)
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terms = State::S1;
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if (GetSize(terms) > 1)
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terms = module->ReduceAnd(NEW_ID, terms);
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return conditions_logic_cache[key] = terms;
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}
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void translate_rd_feedback_to_en(std::string memid, std::vector<RTLIL::Cell*> &rd_ports, std::vector<RTLIL::Cell*> &wr_ports)
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{
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std::map<RTLIL::SigSpec, std::vector<std::set<RTLIL::SigBit>>> async_rd_bits;
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std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
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std::set<RTLIL::SigBit> non_feedback_nets;
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for (auto wire : module->wires())
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if (wire->port_output) {
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std::vector<RTLIL::SigBit> bits = sigmap(wire);
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non_feedback_nets.insert(bits.begin(), bits.end());
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}
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for (auto cell : module->cells())
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{
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bool ignore_data_port = false;
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if (cell->type.in(ID($mux), ID($pmux)))
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{
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std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
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std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
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std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
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std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
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non_feedback_nets.insert(sig_s.begin(), sig_s.end());
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for (int i = 0; i < int(sig_y.size()); i++) {
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muxtree_upstream_map[sig_y[i]].insert(sig_a[i]);
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for (int j = 0; j < int(sig_s.size()); j++)
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muxtree_upstream_map[sig_y[i]].insert(sig_b[i + j*sig_y.size()]);
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}
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continue;
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}
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if (cell->type.in(ID($memwr), ID($memrd)) &&
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cell->parameters.at(ID::MEMID).decode_string() == memid)
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ignore_data_port = true;
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for (auto conn : cell->connections())
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{
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if (ignore_data_port && conn.first == ID::DATA)
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continue;
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std::vector<RTLIL::SigBit> bits = sigmap(conn.second);
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non_feedback_nets.insert(bits.begin(), bits.end());
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}
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}
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std::set<RTLIL::SigBit> expand_non_feedback_nets = non_feedback_nets;
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while (!expand_non_feedback_nets.empty())
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{
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std::set<RTLIL::SigBit> new_expand_non_feedback_nets;
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for (auto &bit : expand_non_feedback_nets)
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if (muxtree_upstream_map.count(bit))
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for (auto &new_bit : muxtree_upstream_map.at(bit))
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if (!non_feedback_nets.count(new_bit)) {
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non_feedback_nets.insert(new_bit);
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new_expand_non_feedback_nets.insert(new_bit);
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}
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expand_non_feedback_nets.swap(new_expand_non_feedback_nets);
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}
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for (auto cell : rd_ports)
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{
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if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
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continue;
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RTLIL::SigSpec sig_addr = sigmap(cell->getPort(ID::ADDR));
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std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort(ID::DATA));
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for (int i = 0; i < int(sig_data.size()); i++)
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if (non_feedback_nets.count(sig_data[i]))
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goto not_pure_feedback_port;
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async_rd_bits[sig_addr].resize(max(async_rd_bits.size(), sig_data.size()));
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for (int i = 0; i < int(sig_data.size()); i++)
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async_rd_bits[sig_addr][i].insert(sig_data[i]);
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not_pure_feedback_port:;
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}
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if (async_rd_bits.empty())
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return;
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log("Populating enable bits on write ports of memory %s.%s with aync read feedback:\n", log_id(module), log_id(memid));
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for (auto cell : wr_ports)
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{
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RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort(ID::ADDR));
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if (!async_rd_bits.count(sig_addr))
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continue;
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log(" Analyzing write port %s.\n", log_id(cell));
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std::vector<RTLIL::SigBit> cell_data = cell->getPort(ID::DATA);
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std::vector<RTLIL::SigBit> cell_en = cell->getPort(ID::EN);
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int created_conditions = 0;
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for (int i = 0; i < int(cell_data.size()); i++)
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if (cell_en[i] != RTLIL::SigBit(RTLIL::State::S0))
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{
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std::map<RTLIL::SigBit, bool> state;
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std::set<std::map<RTLIL::SigBit, bool>> conditions;
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find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions);
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cell_en[i] = conditions_to_logic(conditions, cell_en[i], created_conditions);
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}
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if (created_conditions) {
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log(" Added enable logic for %d different cases.\n", created_conditions);
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cell->setPort(ID::EN, cell_en);
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}
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}
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}
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// -------------
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// Setup and run
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// -------------
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OptMemFeedbackWorker(RTLIL::Design *design) : design(design) {}
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void operator()(RTLIL::Module* module)
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{
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std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
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this->module = module;
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sigmap.set(module);
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sig_to_mux.clear();
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conditions_logic_cache.clear();
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sigmap_xmux = sigmap;
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for (auto cell : module->cells())
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{
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if (cell->type == ID($memrd))
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memindex[cell->parameters.at(ID::MEMID).decode_string()].first.push_back(cell);
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if (cell->type == ID($memwr))
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memindex[cell->parameters.at(ID::MEMID).decode_string()].second.push_back(cell);
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if (cell->type == ID($mux))
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{
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RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
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if (sig_a.is_fully_undef())
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sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
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else if (sig_b.is_fully_undef())
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sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
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}
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if (cell->type.in(ID($mux), ID($pmux)))
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{
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std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
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for (int i = 0; i < int(sig_y.size()); i++)
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sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
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}
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}
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for (auto &it : memindex) {
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std::sort(it.second.first.begin(), it.second.first.end(), memrd_cmp);
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std::sort(it.second.second.begin(), it.second.second.end(), memwr_cmp);
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translate_rd_feedback_to_en(it.first, it.second.first, it.second.second);
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}
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}
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};
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struct OptMemFeedbackPass : public Pass {
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OptMemFeedbackPass() : Pass("opt_mem_feedback", "convert memory read-to-write port feedback paths to write enables") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_mem_feedback [selection]\n");
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log("\n");
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log("This pass detects cases where an asynchronous read port is connected via\n");
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log("a mux tree to a write port with the same address. When such a path is\n");
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log("found, it is replaced with a new condition on an enable signal, possibly\n");
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log("allowing for removal of the read port.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n");
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extra_args(args, 1, design);
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OptMemFeedbackWorker worker(design);
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for (auto module : design->selected_modules())
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worker(module);
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}
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} OptMemFeedbackPass;
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PRIVATE_NAMESPACE_END
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