mirror of https://github.com/YosysHQ/yosys.git
733 lines
13 KiB
Verilog
733 lines
13 KiB
Verilog
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_undefines.v
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//
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// *Module Description:
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// openMSP430 Verilog `undef file
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// BASIC SYSTEM CONFIGURATION
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//----------------------------------------------------------------------------
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// Program Memory sizes
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`ifdef PMEM_SIZE_59_KB
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`undef PMEM_SIZE_59_KB
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`endif
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`ifdef PMEM_SIZE_55_KB
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`undef PMEM_SIZE_55_KB
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`endif
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`ifdef PMEM_SIZE_54_KB
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`undef PMEM_SIZE_54_KB
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`endif
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`ifdef PMEM_SIZE_51_KB
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`undef PMEM_SIZE_51_KB
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`endif
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`ifdef PMEM_SIZE_48_KB
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`undef PMEM_SIZE_48_KB
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`endif
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`ifdef PMEM_SIZE_41_KB
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`undef PMEM_SIZE_41_KB
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`endif
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`ifdef PMEM_SIZE_32_KB
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`undef PMEM_SIZE_32_KB
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`endif
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`ifdef PMEM_SIZE_24_KB
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`undef PMEM_SIZE_24_KB
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`endif
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`ifdef PMEM_SIZE_16_KB
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`undef PMEM_SIZE_16_KB
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`endif
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`ifdef PMEM_SIZE_12_KB
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`undef PMEM_SIZE_12_KB
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`endif
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`ifdef PMEM_SIZE_8_KB
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`undef PMEM_SIZE_8_KB
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`endif
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`ifdef PMEM_SIZE_4_KB
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`undef PMEM_SIZE_4_KB
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`endif
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`ifdef PMEM_SIZE_2_KB
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`undef PMEM_SIZE_2_KB
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`endif
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`ifdef PMEM_SIZE_1_KB
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`undef PMEM_SIZE_1_KB
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`endif
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// Data Memory sizes
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`ifdef DMEM_SIZE_32_KB
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`undef DMEM_SIZE_32_KB
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`endif
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`ifdef DMEM_SIZE_24_KB
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`undef DMEM_SIZE_24_KB
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`endif
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`ifdef DMEM_SIZE_16_KB
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`undef DMEM_SIZE_16_KB
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`endif
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`ifdef DMEM_SIZE_10_KB
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`undef DMEM_SIZE_10_KB
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`endif
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`ifdef DMEM_SIZE_8_KB
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`undef DMEM_SIZE_8_KB
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`endif
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`ifdef DMEM_SIZE_5_KB
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`undef DMEM_SIZE_5_KB
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`endif
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`ifdef DMEM_SIZE_4_KB
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`undef DMEM_SIZE_4_KB
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`endif
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`ifdef DMEM_SIZE_2p5_KB
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`undef DMEM_SIZE_2p5_KB
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`endif
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`ifdef DMEM_SIZE_2_KB
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`undef DMEM_SIZE_2_KB
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`endif
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`ifdef DMEM_SIZE_1_KB
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`undef DMEM_SIZE_1_KB
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`endif
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`ifdef DMEM_SIZE_512_B
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`undef DMEM_SIZE_512_B
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`endif
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`ifdef DMEM_SIZE_256_B
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`undef DMEM_SIZE_256_B
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`endif
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`ifdef DMEM_SIZE_128_B
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`undef DMEM_SIZE_128_B
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`endif
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// Include/Exclude Hardware Multiplier
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`ifdef MULTIPLIER
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`undef MULTIPLIER
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`endif
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// Include Debug interface
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`ifdef DBG_EN
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`undef DBG_EN
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`endif
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//----------------------------------------------------------------------------
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// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
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//----------------------------------------------------------------------------
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// Peripheral Memory Space:
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`ifdef PER_SIZE_32_KB
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`undef PER_SIZE_32_KB
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`endif
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`ifdef PER_SIZE_16_KB
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`undef PER_SIZE_16_KB
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`endif
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`ifdef PER_SIZE_8_KB
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`undef PER_SIZE_8_KB
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`endif
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`ifdef PER_SIZE_4_KB
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`undef PER_SIZE_4_KB
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`endif
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`ifdef PER_SIZE_2_KB
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`undef PER_SIZE_2_KB
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`endif
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`ifdef PER_SIZE_1_KB
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`undef PER_SIZE_1_KB
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`endif
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`ifdef PER_SIZE_512_B
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`undef PER_SIZE_512_B
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`endif
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// Let the CPU break after a PUC occurrence by default
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`ifdef DBG_RST_BRK_EN
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`undef DBG_RST_BRK_EN
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`endif
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// Custom user version number
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`ifdef USER_VERSION
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`undef USER_VERSION
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`endif
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// Include/Exclude Watchdog timer
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`ifdef WATCHDOG
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`undef WATCHDOG
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`endif
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// Include/Exclude Non-Maskable-Interrupt support
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`ifdef NMI
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`undef NMI
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`endif
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//----------------------------------------------------------------------------
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// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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//----------------------------------------------------------------------------
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// Number of hardware breakpoint units
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`ifdef DBG_HWBRK_0
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`undef DBG_HWBRK_0
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`endif
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`ifdef DBG_HWBRK_1
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`undef DBG_HWBRK_1
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`endif
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`ifdef DBG_HWBRK_2
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`undef DBG_HWBRK_2
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`endif
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`ifdef DBG_HWBRK_3
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`undef DBG_HWBRK_3
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`endif
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// Enable/Disable the hardware breakpoint RANGE mode
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`ifdef DBG_HWBRK_RANGE
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`undef DBG_HWBRK_RANGE
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`endif
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// Input synchronizers
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`ifdef SYNC_CPU_EN
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`undef SYNC_CPU_EN
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`endif
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`ifdef SYNC_DBG_EN
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`undef SYNC_DBG_EN
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`endif
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`ifdef SYNC_DBG_UART_RXD
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`undef SYNC_DBG_UART_RXD
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`endif
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`ifdef SYNC_NMI
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`undef SYNC_NMI
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`endif
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// ASIC version
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`ifdef ASIC
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`undef ASIC
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`endif
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//----------------------------------------------------------------------------
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// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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//----------------------------------------------------------------------------
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// Fine grained clock gating
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`ifdef CLOCK_GATING
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`undef CLOCK_GATING
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`endif
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// LFXT clock domain
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`ifdef LFXT_DOMAIN
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`undef LFXT_DOMAIN
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`endif
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// MCLK: Clock Mux
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`ifdef MCLK_MUX
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`undef MCLK_MUX
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`endif
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// SMCLK: Clock Mux
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`ifdef SMCLK_MUX
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`undef SMCLK_MUX
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`endif
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// WATCHDOG: Clock Mux
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`ifdef WATCHDOG_MUX
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`undef WATCHDOG_MUX
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`endif
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// MCLK: Clock divider
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`ifdef MCLK_DIVIDER
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`undef MCLK_DIVIDER
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`endif
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// SMCLK: Clock divider (/1/2/4/8)
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`ifdef SMCLK_DIVIDER
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`undef SMCLK_DIVIDER
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`endif
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// ACLK: Clock divider (/1/2/4/8)
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`ifdef ACLK_DIVIDER
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`undef ACLK_DIVIDER
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`endif
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// LOW POWER MODE: CPUOFF
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`ifdef CPUOFF_EN
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`undef CPUOFF_EN
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`endif
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// LOW POWER MODE: OSCOFF
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`ifdef OSCOFF_EN
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`undef OSCOFF_EN
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`endif
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// LOW POWER MODE: SCG0
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`ifdef SCG0_EN
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`undef SCG0_EN
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`endif
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// LOW POWER MODE: SCG1
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`ifdef SCG1_EN
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`undef SCG1_EN
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`endif
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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// Program Memory Size
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`ifdef PMEM_AWIDTH
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`undef PMEM_AWIDTH
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`endif
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`ifdef PMEM_SIZE
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`undef PMEM_SIZE
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`endif
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// Data Memory Size
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`ifdef DMEM_AWIDTH
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`undef DMEM_AWIDTH
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`endif
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`ifdef DMEM_SIZE
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`undef DMEM_SIZE
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`endif
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// Peripheral Memory Size
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`ifdef PER_AWIDTH
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`undef PER_AWIDTH
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`endif
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`ifdef PER_SIZE
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`undef PER_SIZE
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`endif
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// Data Memory Base Adresses
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`ifdef DMEM_BASE
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`undef DMEM_BASE
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`endif
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// Program & Data Memory most significant address bit (for 16 bit words)
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`ifdef PMEM_MSB
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`undef PMEM_MSB
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`endif
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`ifdef DMEM_MSB
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`undef DMEM_MSB
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`endif
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`ifdef PER_MSB
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`undef PER_MSB
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`endif
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// Instructions type
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`ifdef INST_SO
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`undef INST_SO
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`endif
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`ifdef INST_JMP
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`undef INST_JMP
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`endif
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`ifdef INST_TO
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`undef INST_TO
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`endif
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// Single-operand arithmetic
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`ifdef RRC
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`undef RRC
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`endif
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`ifdef SWPB
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`undef SWPB
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`endif
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`ifdef RRA
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`undef RRA
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`endif
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`ifdef SXT
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`undef SXT
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`endif
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`ifdef PUSH
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`undef PUSH
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`endif
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`ifdef CALL
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`undef CALL
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`endif
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`ifdef RETI
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`undef RETI
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`endif
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`ifdef IRQ
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`undef IRQ
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`endif
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// Conditional jump
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`ifdef JNE
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`undef JNE
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`endif
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`ifdef JEQ
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`undef JEQ
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`endif
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`ifdef JNC
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`undef JNC
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`endif
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`ifdef JC
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`undef JC
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`endif
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`ifdef JN
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`undef JN
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`endif
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`ifdef JGE
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`undef JGE
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`endif
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`ifdef JL
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`undef JL
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`endif
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`ifdef JMP
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`undef JMP
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`endif
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// Two-operand arithmetic
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`ifdef MOV
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`undef MOV
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`endif
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`ifdef ADD
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`undef ADD
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`endif
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`ifdef ADDC
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`undef ADDC
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`endif
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`ifdef SUBC
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`undef SUBC
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`endif
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`ifdef SUB
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`undef SUB
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`endif
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`ifdef CMP
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`undef CMP
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`endif
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`ifdef DADD
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`undef DADD
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`endif
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`ifdef BIT
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`undef BIT
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`endif
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`ifdef BIC
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`undef BIC
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`endif
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`ifdef BIS
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`undef BIS
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`endif
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`ifdef XOR
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`undef XOR
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`endif
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`ifdef AND
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`undef AND
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`endif
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// Addressing modes
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`ifdef DIR
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`undef DIR
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`endif
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`ifdef IDX
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`undef IDX
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`endif
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`ifdef INDIR
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`undef INDIR
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`endif
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`ifdef INDIR_I
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`undef INDIR_I
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`endif
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`ifdef SYMB
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`undef SYMB
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`endif
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`ifdef IMM
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|
`undef IMM
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`endif
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`ifdef ABS
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|
`undef ABS
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|
`endif
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`ifdef CONST
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`undef CONST
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`endif
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|
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// Instruction state machine
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`ifdef I_IRQ_FETCH
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`undef I_IRQ_FETCH
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`endif
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`ifdef I_IRQ_DONE
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|
`undef I_IRQ_DONE
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|
`endif
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|
`ifdef I_DEC
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|
`undef I_DEC
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|
`endif
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`ifdef I_EXT1
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|
`undef I_EXT1
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|
`endif
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|
`ifdef I_EXT2
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|
`undef I_EXT2
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|
`endif
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|
`ifdef I_IDLE
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|
`undef I_IDLE
|
|
`endif
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|
|
// Execution state machine
|
|
`ifdef E_IRQ_0
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|
`undef E_IRQ_0
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`endif
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`ifdef E_IRQ_1
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|
`undef E_IRQ_1
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|
`endif
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|
`ifdef E_IRQ_2
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|
`undef E_IRQ_2
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|
`endif
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|
`ifdef E_IRQ_3
|
|
`undef E_IRQ_3
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|
`endif
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|
`ifdef E_IRQ_4
|
|
`undef E_IRQ_4
|
|
`endif
|
|
`ifdef E_SRC_AD
|
|
`undef E_SRC_AD
|
|
`endif
|
|
`ifdef E_SRC_RD
|
|
`undef E_SRC_RD
|
|
`endif
|
|
`ifdef E_SRC_WR
|
|
`undef E_SRC_WR
|
|
`endif
|
|
`ifdef E_DST_AD
|
|
`undef E_DST_AD
|
|
`endif
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|
`ifdef E_DST_RD
|
|
`undef E_DST_RD
|
|
`endif
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|
`ifdef E_DST_WR
|
|
`undef E_DST_WR
|
|
`endif
|
|
`ifdef E_EXEC
|
|
`undef E_EXEC
|
|
`endif
|
|
`ifdef E_JUMP
|
|
`undef E_JUMP
|
|
`endif
|
|
`ifdef E_IDLE
|
|
`undef E_IDLE
|
|
`endif
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|
|
|
// ALU control signals
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|
`ifdef ALU_SRC_INV
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|
`undef ALU_SRC_INV
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|
`endif
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|
`ifdef ALU_INC
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|
`undef ALU_INC
|
|
`endif
|
|
`ifdef ALU_INC_C
|
|
`undef ALU_INC_C
|
|
`endif
|
|
`ifdef ALU_ADD
|
|
`undef ALU_ADD
|
|
`endif
|
|
`ifdef ALU_AND
|
|
`undef ALU_AND
|
|
`endif
|
|
`ifdef ALU_OR
|
|
`undef ALU_OR
|
|
`endif
|
|
`ifdef ALU_XOR
|
|
`undef ALU_XOR
|
|
`endif
|
|
`ifdef ALU_DADD
|
|
`undef ALU_DADD
|
|
`endif
|
|
`ifdef ALU_STAT_7
|
|
`undef ALU_STAT_7
|
|
`endif
|
|
`ifdef ALU_STAT_F
|
|
`undef ALU_STAT_F
|
|
`endif
|
|
`ifdef ALU_SHIFT
|
|
`undef ALU_SHIFT
|
|
`endif
|
|
`ifdef EXEC_NO_WR
|
|
`undef EXEC_NO_WR
|
|
`endif
|
|
|
|
// Debug interface
|
|
`ifdef DBG_UART_WR
|
|
`undef DBG_UART_WR
|
|
`endif
|
|
`ifdef DBG_UART_BW
|
|
`undef DBG_UART_BW
|
|
`endif
|
|
`ifdef DBG_UART_ADDR
|
|
`undef DBG_UART_ADDR
|
|
`endif
|
|
|
|
// Debug interface CPU_CTL register
|
|
`ifdef HALT
|
|
`undef HALT
|
|
`endif
|
|
`ifdef RUN
|
|
`undef RUN
|
|
`endif
|
|
`ifdef ISTEP
|
|
`undef ISTEP
|
|
`endif
|
|
`ifdef SW_BRK_EN
|
|
`undef SW_BRK_EN
|
|
`endif
|
|
`ifdef FRZ_BRK_EN
|
|
`undef FRZ_BRK_EN
|
|
`endif
|
|
`ifdef RST_BRK_EN
|
|
`undef RST_BRK_EN
|
|
`endif
|
|
`ifdef CPU_RST
|
|
`undef CPU_RST
|
|
`endif
|
|
|
|
// Debug interface CPU_STAT register
|
|
`ifdef HALT_RUN
|
|
`undef HALT_RUN
|
|
`endif
|
|
`ifdef PUC_PND
|
|
`undef PUC_PND
|
|
`endif
|
|
`ifdef SWBRK_PND
|
|
`undef SWBRK_PND
|
|
`endif
|
|
`ifdef HWBRK0_PND
|
|
`undef HWBRK0_PND
|
|
`endif
|
|
`ifdef HWBRK1_PND
|
|
`undef HWBRK1_PND
|
|
`endif
|
|
|
|
// Debug interface BRKx_CTL register
|
|
`ifdef BRK_MODE_RD
|
|
`undef BRK_MODE_RD
|
|
`endif
|
|
`ifdef BRK_MODE_WR
|
|
`undef BRK_MODE_WR
|
|
`endif
|
|
`ifdef BRK_MODE
|
|
`undef BRK_MODE
|
|
`endif
|
|
`ifdef BRK_EN
|
|
`undef BRK_EN
|
|
`endif
|
|
`ifdef BRK_I_EN
|
|
`undef BRK_I_EN
|
|
`endif
|
|
`ifdef BRK_RANGE
|
|
`undef BRK_RANGE
|
|
`endif
|
|
|
|
// Basic clock module: BCSCTL1 Control Register
|
|
`ifdef DIVAx
|
|
`undef DIVAx
|
|
`endif
|
|
|
|
// Basic clock module: BCSCTL2 Control Register
|
|
`ifdef SELMx
|
|
`undef SELMx
|
|
`endif
|
|
`ifdef DIVMx
|
|
`undef DIVMx
|
|
`endif
|
|
`ifdef SELS
|
|
`undef SELS
|
|
`endif
|
|
`ifdef DIVSx
|
|
`undef DIVSx
|
|
`endif
|
|
|
|
// MCLK Clock gate
|
|
`ifdef MCLK_CGATE
|
|
`undef MCLK_CGATE
|
|
`endif
|
|
|
|
// SMCLK Clock gate
|
|
`ifdef SMCLK_CGATE
|
|
`undef SMCLK_CGATE
|
|
`endif
|
|
|
|
//
|
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
|
//======================================
|
|
|
|
// Debug interface: CPU version
|
|
`ifdef CPU_VERSION
|
|
`undef CPU_VERSION
|
|
`endif
|
|
|
|
// Debug interface: Software breakpoint opcode
|
|
`ifdef DBG_SWBRK_OP
|
|
`undef DBG_SWBRK_OP
|
|
`endif
|
|
|
|
// Debug UART interface auto data synchronization
|
|
`ifdef DBG_UART_AUTO_SYNC
|
|
`undef DBG_UART_AUTO_SYNC
|
|
`endif
|
|
|
|
// Debug UART interface data rate
|
|
`ifdef DBG_UART_BAUD
|
|
`undef DBG_UART_BAUD
|
|
`endif
|
|
`ifdef DBG_DCO_FREQ
|
|
`undef DBG_DCO_FREQ
|
|
`endif
|
|
`ifdef DBG_UART_CNT
|
|
`undef DBG_UART_CNT
|
|
`endif
|
|
|
|
// Debug interface selection
|
|
`ifdef DBG_UART
|
|
`undef DBG_UART
|
|
`endif
|
|
`ifdef DBG_JTAG
|
|
`undef DBG_JTAG
|
|
`endif
|
|
|
|
// Enable/Disable the hardware breakpoint RANGE mode
|
|
`ifdef HWBRK_RANGE
|
|
`undef HWBRK_RANGE
|
|
`endif
|
|
|
|
// Counter width for the debug interface UART
|
|
`ifdef DBG_UART_XFER_CNT_W
|
|
`undef DBG_UART_XFER_CNT_W
|
|
`endif
|
|
|
|
//
|
|
// MULTIPLIER CONFIGURATION
|
|
//======================================
|
|
|
|
`ifdef MPY_16x16
|
|
`undef MPY_16x16
|
|
`endif
|