mirror of https://github.com/YosysHQ/yosys.git
844 lines
26 KiB
Verilog
844 lines
26 KiB
Verilog
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_defines.v
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//
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// *Module Description:
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// openMSP430 Configuration file
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 151 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-07-23 00:24:11 +0200 (Mon, 23 Jul 2012) $
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//----------------------------------------------------------------------------
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//`define OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_undefines.v"
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`endif
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//============================================================================
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//============================================================================
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// BASIC SYSTEM CONFIGURATION
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//============================================================================
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//============================================================================
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//
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// Note: the sum of program, data and peripheral memory spaces must not
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// exceed 64 kB
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//
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// Program Memory Size:
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// Uncomment the required memory size
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//-------------------------------------------------------
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//`define PMEM_SIZE_CUSTOM
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//`define PMEM_SIZE_59_KB
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//`define PMEM_SIZE_55_KB
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//`define PMEM_SIZE_54_KB
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//`define PMEM_SIZE_51_KB
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//`define PMEM_SIZE_48_KB
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//`define PMEM_SIZE_41_KB
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//`define PMEM_SIZE_32_KB
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//`define PMEM_SIZE_24_KB
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//`define PMEM_SIZE_16_KB
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//`define PMEM_SIZE_12_KB
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//`define PMEM_SIZE_8_KB
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//`define PMEM_SIZE_4_KB
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`define PMEM_SIZE_2_KB
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//`define PMEM_SIZE_1_KB
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// Data Memory Size:
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// Uncomment the required memory size
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//-------------------------------------------------------
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//`define DMEM_SIZE_CUSTOM
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//`define DMEM_SIZE_32_KB
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//`define DMEM_SIZE_24_KB
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//`define DMEM_SIZE_16_KB
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//`define DMEM_SIZE_10_KB
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//`define DMEM_SIZE_8_KB
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//`define DMEM_SIZE_5_KB
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//`define DMEM_SIZE_4_KB
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//`define DMEM_SIZE_2p5_KB
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//`define DMEM_SIZE_2_KB
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//`define DMEM_SIZE_1_KB
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//`define DMEM_SIZE_512_B
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//`define DMEM_SIZE_256_B
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`define DMEM_SIZE_128_B
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// Include/Exclude Hardware Multiplier
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`define MULTIPLIER
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// Include/Exclude Serial Debug interface
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`define DBG_EN
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//============================================================================
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//============================================================================
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// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
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//============================================================================
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//============================================================================
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//-------------------------------------------------------
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// Custom user version number
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//-------------------------------------------------------
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// This 5 bit field can be freely used in order to allow
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// custom identification of the system through the debug
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// interface.
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// (see CPU_ID.USER_VERSION field in the documentation)
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//-------------------------------------------------------
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`define USER_VERSION 5'b00000
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//-------------------------------------------------------
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// Include/Exclude Watchdog timer
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//-------------------------------------------------------
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// When excluded, the following functionality will be
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// lost:
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// - Watchog (both interval and watchdog modes)
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// - NMI interrupt edge selection
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// - Possibility to generate a software PUC reset
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//-------------------------------------------------------
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`define WATCHDOG
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///-------------------------------------------------------
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// Include/Exclude Non-Maskable-Interrupt support
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//-------------------------------------------------------
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`define NMI
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//-------------------------------------------------------
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// Input synchronizers
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//-------------------------------------------------------
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// In some cases, the asynchronous input ports might
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// already be synchronized externally.
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// If an extensive CDC design review showed that this
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// is really the case, the individual synchronizers
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// can be disabled with the following defines.
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//
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// Notes:
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// - all three signals are all sampled in the MCLK domain
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//
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// - the dbg_en signal reset the debug interface
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// when 0. Therefore make sure it is glitch free.
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//
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//-------------------------------------------------------
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`define SYNC_NMI
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//`define SYNC_CPU_EN
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//`define SYNC_DBG_EN
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//-------------------------------------------------------
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// Peripheral Memory Space:
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//-------------------------------------------------------
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// The original MSP430 architecture map the peripherals
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// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
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// The following defines allow you to expand this space
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// up to 32 kB (i.e. from 0x0000 to 0x7fff).
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// As a consequence, the data memory mapping will be
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// shifted up and a custom linker script will therefore
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// be required by the GCC compiler.
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//-------------------------------------------------------
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//`define PER_SIZE_CUSTOM
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//`define PER_SIZE_32_KB
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//`define PER_SIZE_16_KB
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//`define PER_SIZE_8_KB
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//`define PER_SIZE_4_KB
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//`define PER_SIZE_2_KB
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//`define PER_SIZE_1_KB
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`define PER_SIZE_512_B
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//-------------------------------------------------------
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// Defines the debugger CPU_CTL.RST_BRK_EN reset value
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// (CPU break on PUC reset)
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//-------------------------------------------------------
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// When defined, the CPU will automatically break after
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// a PUC occurrence by default. This is typically useful
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// when the program memory can only be initialized through
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// the serial debug interface.
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//-------------------------------------------------------
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`define DBG_RST_BRK_EN
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//============================================================================
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//============================================================================
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// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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//============================================================================
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//============================================================================
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//
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// IMPORTANT NOTE: Please update following configuration options ONLY if
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// you have a good reason to do so... and if you know what
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// you are doing :-P
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//
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//============================================================================
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//-------------------------------------------------------
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// Number of hardware breakpoint/watchpoint units
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// (each unit contains two hardware addresses available
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// for breakpoints or watchpoints):
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// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
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// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
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//-------------------------------------------------------
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// Please keep in mind that hardware breakpoints only
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// make sense whenever the program memory is not an SRAM
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// (i.e. Flash/OTP/ROM/...) or when you are interested
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// in data breakpoints.
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//-------------------------------------------------------
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//`define DBG_HWBRK_0
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//`define DBG_HWBRK_1
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//`define DBG_HWBRK_2
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//`define DBG_HWBRK_3
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//-------------------------------------------------------
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// Enable/Disable the hardware breakpoint RANGE mode
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//-------------------------------------------------------
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// When enabled this feature allows the hardware breakpoint
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// units to stop the cpu whenever an instruction or data
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// access lays within an address range.
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// Note that this feature is not supported by GDB.
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//-------------------------------------------------------
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//`define DBG_HWBRK_RANGE
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//-------------------------------------------------------
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// Custom Program/Data and Peripheral Memory Spaces
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//-------------------------------------------------------
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// The following values are valid only if the
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// corresponding *_SIZE_CUSTOM defines are uncommented:
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//
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// - *_SIZE : size of the section in bytes.
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// - *_AWIDTH : address port width, this value must allow
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// to address all WORDS of the section
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// (i.e. the *_SIZE divided by 2)
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//-------------------------------------------------------
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// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
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`define PMEM_CUSTOM_AWIDTH 10
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`define PMEM_CUSTOM_SIZE 2028
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// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
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`define DMEM_CUSTOM_AWIDTH 6
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`define DMEM_CUSTOM_SIZE 128
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// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
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`define PER_CUSTOM_AWIDTH 8
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`define PER_CUSTOM_SIZE 512
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//-------------------------------------------------------
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// ASIC version
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// ASIC system configuration section (see below) and
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// will activate scan support for production test.
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//
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// WARNING: if you target an FPGA, leave this define
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// commented.
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//-------------------------------------------------------
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//`define ASIC
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//============================================================================
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//============================================================================
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// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
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//============================================================================
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//============================================================================
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`ifdef ASIC
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//===============================================================
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// FINE GRAINED CLOCK GATING
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//===============================================================
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//-------------------------------------------------------
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// When uncommented, this define will enable the fine
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// grained clock gating of all registers in the core.
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//-------------------------------------------------------
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`define CLOCK_GATING
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//===============================================================
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// LFXT CLOCK DOMAIN
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//===============================================================
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//-------------------------------------------------------
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// When uncommented, this define will enable the lfxt_clk
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// clock domain.
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// When commented out, the whole chip is clocked with dco_clk.
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//-------------------------------------------------------
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`define LFXT_DOMAIN
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//===============================================================
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// CLOCK MUXES
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//===============================================================
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//-------------------------------------------------------
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// MCLK: Clock Mux
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// MCLK clock MUX allowing the selection between
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// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
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// When commented, DCO_CLK is selected.
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//-------------------------------------------------------
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`define MCLK_MUX
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//-------------------------------------------------------
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// SMCLK: Clock Mux
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// SMCLK clock MUX allowing the selection between
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// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
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// When commented, DCO_CLK is selected.
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//-------------------------------------------------------
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`define SMCLK_MUX
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//-------------------------------------------------------
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// WATCHDOG: Clock Mux
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// Watchdog clock MUX allowing the selection between
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// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
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// When commented out, ACLK is selected if the
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// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
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// selected otherwise.
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//-------------------------------------------------------
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`define WATCHDOG_MUX
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//`define WATCHDOG_NOMUX_ACLK
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//===============================================================
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// CLOCK DIVIDERS
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//===============================================================
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//-------------------------------------------------------
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// MCLK: Clock divider
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// MCLK clock divider (/1/2/4/8)
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//-------------------------------------------------------
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`define MCLK_DIVIDER
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//-------------------------------------------------------
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// SMCLK: Clock divider (/1/2/4/8)
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// SMCLK clock divider
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//-------------------------------------------------------
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`define SMCLK_DIVIDER
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//-------------------------------------------------------
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// ACLK: Clock divider (/1/2/4/8)
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// ACLK clock divider
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//-------------------------------------------------------
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`define ACLK_DIVIDER
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//===============================================================
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// LOW POWER MODES
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//===============================================================
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//-------------------------------------------------------
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// LOW POWER MODE: CPUOFF
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//-------------------------------------------------------
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// When uncommented, this define will include the
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// clock gate allowing to switch off MCLK in
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// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
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//-------------------------------------------------------
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`define CPUOFF_EN
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//-------------------------------------------------------
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// LOW POWER MODE: SCG0
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// DCO_ENABLE/WKUP port control (always 1 when commented).
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// This allows to switch off the DCO oscillator in the
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// following low power modes: LPM1, LPM3, LPM4
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//-------------------------------------------------------
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`define SCG0_EN
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//-------------------------------------------------------
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// LOW POWER MODE: SCG1
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//-------------------------------------------------------
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// When uncommented, this define will include the
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// clock gate allowing to switch off SMCLK in
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// the following low power modes: LPM2, LPM3, LPM4
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//-------------------------------------------------------
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`define SCG1_EN
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//-------------------------------------------------------
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// LOW POWER MODE: OSCOFF
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//-------------------------------------------------------
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// When uncommented, this define will include the
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// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
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// port control (always 1 when commented).
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// This allows to switch off the low frequency oscillator
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// in the following low power modes: LPM4
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//-------------------------------------------------------
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`define OSCOFF_EN
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`endif
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//
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// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
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//==================================================
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// Program Memory Size
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`ifdef PMEM_SIZE_59_KB
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`define PMEM_AWIDTH 15
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`define PMEM_SIZE 60416
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`endif
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`ifdef PMEM_SIZE_55_KB
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`define PMEM_AWIDTH 15
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`define PMEM_SIZE 56320
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`endif
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`ifdef PMEM_SIZE_54_KB
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`define PMEM_AWIDTH 15
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`define PMEM_SIZE 55296
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`endif
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`ifdef PMEM_SIZE_51_KB
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`define PMEM_AWIDTH 15
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`define PMEM_SIZE 52224
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`endif
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`ifdef PMEM_SIZE_48_KB
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`define PMEM_AWIDTH 15
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`define PMEM_SIZE 49152
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`endif
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`ifdef PMEM_SIZE_41_KB
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`define PMEM_AWIDTH 15
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`define PMEM_SIZE 41984
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`endif
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`ifdef PMEM_SIZE_32_KB
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`define PMEM_AWIDTH 14
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`define PMEM_SIZE 32768
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`endif
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`ifdef PMEM_SIZE_24_KB
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`define PMEM_AWIDTH 14
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`define PMEM_SIZE 24576
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`endif
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`ifdef PMEM_SIZE_16_KB
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`define PMEM_AWIDTH 13
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`define PMEM_SIZE 16384
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`endif
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`ifdef PMEM_SIZE_12_KB
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`define PMEM_AWIDTH 13
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`define PMEM_SIZE 12288
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`endif
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`ifdef PMEM_SIZE_8_KB
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`define PMEM_AWIDTH 12
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`define PMEM_SIZE 8192
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`endif
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`ifdef PMEM_SIZE_4_KB
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`define PMEM_AWIDTH 11
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`define PMEM_SIZE 4096
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`endif
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`ifdef PMEM_SIZE_2_KB
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`define PMEM_AWIDTH 10
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`define PMEM_SIZE 2048
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`endif
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`ifdef PMEM_SIZE_1_KB
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`define PMEM_AWIDTH 9
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`define PMEM_SIZE 1024
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`endif
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`ifdef PMEM_SIZE_CUSTOM
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`define PMEM_AWIDTH `PMEM_CUSTOM_AWIDTH
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`define PMEM_SIZE `PMEM_CUSTOM_SIZE
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`endif
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|
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// Data Memory Size
|
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`ifdef DMEM_SIZE_32_KB
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`define DMEM_AWIDTH 14
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`define DMEM_SIZE 32768
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`endif
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`ifdef DMEM_SIZE_24_KB
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`define DMEM_AWIDTH 14
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`define DMEM_SIZE 24576
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`endif
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`ifdef DMEM_SIZE_16_KB
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`define DMEM_AWIDTH 13
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`define DMEM_SIZE 16384
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`endif
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`ifdef DMEM_SIZE_10_KB
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`define DMEM_AWIDTH 13
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`define DMEM_SIZE 10240
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`endif
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`ifdef DMEM_SIZE_8_KB
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`define DMEM_AWIDTH 12
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`define DMEM_SIZE 8192
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`endif
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`ifdef DMEM_SIZE_5_KB
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`define DMEM_AWIDTH 12
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`define DMEM_SIZE 5120
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`endif
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`ifdef DMEM_SIZE_4_KB
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`define DMEM_AWIDTH 11
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`define DMEM_SIZE 4096
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`endif
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`ifdef DMEM_SIZE_2p5_KB
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`define DMEM_AWIDTH 11
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`define DMEM_SIZE 2560
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`endif
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`ifdef DMEM_SIZE_2_KB
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`define DMEM_AWIDTH 10
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`define DMEM_SIZE 2048
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`endif
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`ifdef DMEM_SIZE_1_KB
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`define DMEM_AWIDTH 9
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`define DMEM_SIZE 1024
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`endif
|
|
`ifdef DMEM_SIZE_512_B
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`define DMEM_AWIDTH 8
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`define DMEM_SIZE 512
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`endif
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`ifdef DMEM_SIZE_256_B
|
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`define DMEM_AWIDTH 7
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`define DMEM_SIZE 256
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`endif
|
|
`ifdef DMEM_SIZE_128_B
|
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`define DMEM_AWIDTH 6
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`define DMEM_SIZE 128
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`endif
|
|
`ifdef DMEM_SIZE_CUSTOM
|
|
`define DMEM_AWIDTH `DMEM_CUSTOM_AWIDTH
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`define DMEM_SIZE `DMEM_CUSTOM_SIZE
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|
`endif
|
|
|
|
// Peripheral Memory Size
|
|
`ifdef PER_SIZE_32_KB
|
|
`define PER_AWIDTH 14
|
|
`define PER_SIZE 32768
|
|
`endif
|
|
`ifdef PER_SIZE_16_KB
|
|
`define PER_AWIDTH 13
|
|
`define PER_SIZE 16384
|
|
`endif
|
|
`ifdef PER_SIZE_8_KB
|
|
`define PER_AWIDTH 12
|
|
`define PER_SIZE 8192
|
|
`endif
|
|
`ifdef PER_SIZE_4_KB
|
|
`define PER_AWIDTH 11
|
|
`define PER_SIZE 4096
|
|
`endif
|
|
`ifdef PER_SIZE_2_KB
|
|
`define PER_AWIDTH 10
|
|
`define PER_SIZE 2048
|
|
`endif
|
|
`ifdef PER_SIZE_1_KB
|
|
`define PER_AWIDTH 9
|
|
`define PER_SIZE 1024
|
|
`endif
|
|
`ifdef PER_SIZE_512_B
|
|
`define PER_AWIDTH 8
|
|
`define PER_SIZE 512
|
|
`endif
|
|
`ifdef PER_SIZE_CUSTOM
|
|
`define PER_AWIDTH `PER_CUSTOM_AWIDTH
|
|
`define PER_SIZE `PER_CUSTOM_SIZE
|
|
`endif
|
|
|
|
// Data Memory Base Adresses
|
|
`define DMEM_BASE `PER_SIZE
|
|
|
|
// Program & Data Memory most significant address bit (for 16 bit words)
|
|
`define PMEM_MSB `PMEM_AWIDTH-1
|
|
`define DMEM_MSB `DMEM_AWIDTH-1
|
|
`define PER_MSB `PER_AWIDTH-1
|
|
|
|
//
|
|
// STATES, REGISTER FIELDS, ...
|
|
//======================================
|
|
|
|
// Instructions type
|
|
`define INST_SO 0
|
|
`define INST_JMP 1
|
|
`define INST_TO 2
|
|
|
|
// Single-operand arithmetic
|
|
`define RRC 0
|
|
`define SWPB 1
|
|
`define RRA 2
|
|
`define SXT 3
|
|
`define PUSH 4
|
|
`define CALL 5
|
|
`define RETI 6
|
|
`define IRQ 7
|
|
|
|
// Conditional jump
|
|
`define JNE 0
|
|
`define JEQ 1
|
|
`define JNC 2
|
|
`define JC 3
|
|
`define JN 4
|
|
`define JGE 5
|
|
`define JL 6
|
|
`define JMP 7
|
|
|
|
// Two-operand arithmetic
|
|
`define MOV 0
|
|
`define ADD 1
|
|
`define ADDC 2
|
|
`define SUBC 3
|
|
`define SUB 4
|
|
`define CMP 5
|
|
`define DADD 6
|
|
`define BIT 7
|
|
`define BIC 8
|
|
`define BIS 9
|
|
`define XOR 10
|
|
`define AND 11
|
|
|
|
// Addressing modes
|
|
`define DIR 0
|
|
`define IDX 1
|
|
`define INDIR 2
|
|
`define INDIR_I 3
|
|
`define SYMB 4
|
|
`define IMM 5
|
|
`define ABS 6
|
|
`define CONST 7
|
|
|
|
// Instruction state machine
|
|
`define I_IRQ_FETCH 3'h0
|
|
`define I_IRQ_DONE 3'h1
|
|
`define I_DEC 3'h2
|
|
`define I_EXT1 3'h3
|
|
`define I_EXT2 3'h4
|
|
`define I_IDLE 3'h5
|
|
|
|
// Execution state machine
|
|
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
|
|
`define E_IRQ_0 4'h2
|
|
`define E_IRQ_1 4'h1
|
|
`define E_IRQ_2 4'h0
|
|
`define E_IRQ_3 4'h3
|
|
`define E_IRQ_4 4'h4
|
|
`define E_SRC_AD 4'h5
|
|
`define E_SRC_RD 4'h6
|
|
`define E_SRC_WR 4'h7
|
|
`define E_DST_AD 4'h8
|
|
`define E_DST_RD 4'h9
|
|
`define E_DST_WR 4'hA
|
|
`define E_EXEC 4'hB
|
|
`define E_JUMP 4'hC
|
|
`define E_IDLE 4'hD
|
|
|
|
// ALU control signals
|
|
`define ALU_SRC_INV 0
|
|
`define ALU_INC 1
|
|
`define ALU_INC_C 2
|
|
`define ALU_ADD 3
|
|
`define ALU_AND 4
|
|
`define ALU_OR 5
|
|
`define ALU_XOR 6
|
|
`define ALU_DADD 7
|
|
`define ALU_STAT_7 8
|
|
`define ALU_STAT_F 9
|
|
`define ALU_SHIFT 10
|
|
`define EXEC_NO_WR 11
|
|
|
|
// Debug interface
|
|
`define DBG_UART_WR 18
|
|
`define DBG_UART_BW 17
|
|
`define DBG_UART_ADDR 16:11
|
|
|
|
// Debug interface CPU_CTL register
|
|
`define HALT 0
|
|
`define RUN 1
|
|
`define ISTEP 2
|
|
`define SW_BRK_EN 3
|
|
`define FRZ_BRK_EN 4
|
|
`define RST_BRK_EN 5
|
|
`define CPU_RST 6
|
|
|
|
// Debug interface CPU_STAT register
|
|
`define HALT_RUN 0
|
|
`define PUC_PND 1
|
|
`define SWBRK_PND 3
|
|
`define HWBRK0_PND 4
|
|
`define HWBRK1_PND 5
|
|
|
|
// Debug interface BRKx_CTL register
|
|
`define BRK_MODE_RD 0
|
|
`define BRK_MODE_WR 1
|
|
`define BRK_MODE 1:0
|
|
`define BRK_EN 2
|
|
`define BRK_I_EN 3
|
|
`define BRK_RANGE 4
|
|
|
|
// Basic clock module: BCSCTL1 Control Register
|
|
`define DIVAx 5:4
|
|
|
|
// Basic clock module: BCSCTL2 Control Register
|
|
`define SELMx 7
|
|
`define DIVMx 5:4
|
|
`define SELS 3
|
|
`define DIVSx 2:1
|
|
|
|
// MCLK Clock gate
|
|
`ifdef CPUOFF_EN
|
|
`define MCLK_CGATE
|
|
`else
|
|
`ifdef MCLK_DIVIDER
|
|
`define MCLK_CGATE
|
|
`endif
|
|
`endif
|
|
|
|
// SMCLK Clock gate
|
|
`ifdef SCG1_EN
|
|
`define SMCLK_CGATE
|
|
`else
|
|
`ifdef SMCLK_DIVIDER
|
|
`define SMCLK_CGATE
|
|
`endif
|
|
`endif
|
|
|
|
//
|
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
|
//======================================
|
|
|
|
// Debug interface: CPU version
|
|
`define CPU_VERSION 3'h2
|
|
|
|
// Debug interface: Software breakpoint opcode
|
|
`define DBG_SWBRK_OP 16'h4343
|
|
|
|
// Debug UART interface auto data synchronization
|
|
// If the following define is commented out, then
|
|
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
|
|
// defined.
|
|
`define DBG_UART_AUTO_SYNC
|
|
|
|
// Debug UART interface data rate
|
|
// In order to properly setup the UART debug interface, you
|
|
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
|
|
// the chosen BAUD rate from the UART interface.
|
|
//
|
|
//`define DBG_UART_BAUD 9600
|
|
//`define DBG_UART_BAUD 19200
|
|
//`define DBG_UART_BAUD 38400
|
|
//`define DBG_UART_BAUD 57600
|
|
//`define DBG_UART_BAUD 115200
|
|
//`define DBG_UART_BAUD 230400
|
|
//`define DBG_UART_BAUD 460800
|
|
//`define DBG_UART_BAUD 576000
|
|
//`define DBG_UART_BAUD 921600
|
|
`define DBG_UART_BAUD 2000000
|
|
`define DBG_DCO_FREQ 20000000
|
|
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
|
|
|
|
// Debug interface selection
|
|
// `define DBG_UART -> Enable UART (8N1) debug interface
|
|
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
|
|
//
|
|
`define DBG_UART
|
|
//`define DBG_JTAG
|
|
|
|
// Debug interface input synchronizer
|
|
`define SYNC_DBG_UART_RXD
|
|
|
|
// Enable/Disable the hardware breakpoint RANGE mode
|
|
`ifdef DBG_HWBRK_RANGE
|
|
`define HWBRK_RANGE 1'b1
|
|
`else
|
|
`define HWBRK_RANGE 1'b0
|
|
`endif
|
|
|
|
// Counter width for the debug interface UART
|
|
`define DBG_UART_XFER_CNT_W 16
|
|
|
|
// Check configuration
|
|
`ifdef DBG_EN
|
|
`ifdef DBG_UART
|
|
`ifdef DBG_JTAG
|
|
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
|
|
`endif
|
|
`else
|
|
`ifdef DBG_JTAG
|
|
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
|
|
`else
|
|
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
|
|
`endif
|
|
`endif
|
|
`endif
|
|
|
|
//
|
|
// MULTIPLIER CONFIGURATION
|
|
//======================================
|
|
|
|
// If uncommented, the following define selects
|
|
// the 16x16 multiplier (1 cycle) instead of the
|
|
// default 16x8 multplier (2 cycles)
|
|
//`define MPY_16x16
|
|
|
|
//======================================
|
|
// CONFIGURATION CHECKS
|
|
//======================================
|
|
`ifdef LFXT_DOMAIN
|
|
`else
|
|
`ifdef MCLK_MUX
|
|
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`ifdef SMCLK_MUX
|
|
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`ifdef WATCHDOG_MUX
|
|
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`else
|
|
`ifdef WATCHDOG_NOMUX_ACLK
|
|
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`endif
|
|
`ifdef OSCOFF_EN
|
|
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`endif
|