mirror of https://github.com/YosysHQ/yosys.git
354 lines
13 KiB
Verilog
354 lines
13 KiB
Verilog
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_sfr.v
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//
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// *Module Description:
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// Processor Special function register
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// Non-Maskable Interrupt generation
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_defines.v"
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`endif
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module omsp_sfr (
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// OUTPUTs
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cpu_id, // CPU ID
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nmi_pnd, // NMI Pending
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nmi_wkup, // NMI Wakeup
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per_dout, // Peripheral data output
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wdtie, // Watchdog-timer interrupt enable
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wdtifg_sw_clr, // Watchdog-timer interrupt flag software clear
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wdtifg_sw_set, // Watchdog-timer interrupt flag software set
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// INPUTs
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mclk, // Main system clock
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nmi, // Non-maskable interrupt (asynchronous)
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nmi_acc, // Non-Maskable interrupt request accepted
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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puc_rst, // Main system reset
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scan_mode, // Scan mode
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wdtifg, // Watchdog-timer interrupt flag
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wdtnmies // Watchdog-timer NMI edge selection
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);
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// OUTPUTs
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//=========
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output [31:0] cpu_id; // CPU ID
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output nmi_pnd; // NMI Pending
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output nmi_wkup; // NMI Wakeup
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output [15:0] per_dout; // Peripheral data output
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output wdtie; // Watchdog-timer interrupt enable
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output wdtifg_sw_clr;// Watchdog-timer interrupt flag software clear
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output wdtifg_sw_set;// Watchdog-timer interrupt flag software set
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// INPUTs
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//=========
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input mclk; // Main system clock
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input nmi; // Non-maskable interrupt (asynchronous)
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input nmi_acc; // Non-Maskable interrupt request accepted
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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input scan_mode; // Scan mode
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input wdtifg; // Watchdog-timer interrupt flag
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input wdtnmies; // Watchdog-timer NMI edge selection
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//=============================================================================
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// 1) PARAMETER DECLARATION
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//=============================================================================
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// Register base address (must be aligned to decoder bit width)
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parameter [14:0] BASE_ADDR = 15'h0000;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 3;
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// Register addresses offset
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parameter [DEC_WD-1:0] IE1 = 'h0,
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IFG1 = 'h2,
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CPU_ID_LO = 'h4,
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CPU_ID_HI = 'h6;
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// Register one-hot decoder utilities
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parameter DEC_SZ = (1 << DEC_WD);
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1),
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IFG1_D = (BASE_REG << IFG1),
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CPU_ID_LO_D = (BASE_REG << CPU_ID_LO),
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CPU_ID_HI_D = (BASE_REG << CPU_ID_HI);
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//============================================================================
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// 2) REGISTER DECODER
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//============================================================================
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
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// Register address decode
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wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) |
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(IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}}) |
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(CPU_ID_LO_D & {DEC_SZ{(reg_addr==(CPU_ID_LO >>1))}}) |
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(CPU_ID_HI_D & {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}});
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// Read/Write probes
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wire reg_lo_write = per_we[0] & reg_sel;
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wire reg_hi_write = per_we[1] & reg_sel;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
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wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// IE1 Register
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//--------------
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wire [7:0] ie1;
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wire ie1_wr = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1];
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wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0];
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`ifdef NMI
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reg nmie;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) nmie <= 1'b0;
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else if (nmi_acc) nmie <= 1'b0;
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else if (ie1_wr) nmie <= ie1_nxt[4];
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`else
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wire nmie = 1'b0;
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`endif
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`ifdef WATCHDOG
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reg wdtie;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) wdtie <= 1'b0;
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else if (ie1_wr) wdtie <= ie1_nxt[0];
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`else
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wire wdtie = 1'b0;
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`endif
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assign ie1 = {3'b000, nmie, 3'b000, wdtie};
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// IFG1 Register
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//---------------
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wire [7:0] ifg1;
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wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1];
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wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0];
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`ifdef NMI
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reg nmiifg;
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wire nmi_edge;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) nmiifg <= 1'b0;
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else if (nmi_edge) nmiifg <= 1'b1;
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else if (ifg1_wr) nmiifg <= ifg1_nxt[4];
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`else
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wire nmiifg = 1'b0;
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`endif
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`ifdef WATCHDOG
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assign wdtifg_sw_clr = ifg1_wr & ~ifg1_nxt[0];
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assign wdtifg_sw_set = ifg1_wr & ifg1_nxt[0];
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`else
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assign wdtifg_sw_clr = 1'b0;
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assign wdtifg_sw_set = 1'b0;
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`endif
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assign ifg1 = {3'b000, nmiifg, 3'b000, wdtifg};
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// CPU_ID Register (READ ONLY)
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//-----------------------------
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// -------------------------------------------------------------------
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// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
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// |----------------------------+-----------------+------+-------------|
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// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
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// --------------------------------------------------------------------
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// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
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// |----------------------------+-------------------------------+------|
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// | PMEM_SIZE | DMEM_SIZE | MPY |
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// -------------------------------------------------------------------
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wire [2:0] cpu_version = `CPU_VERSION;
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`ifdef ASIC
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wire cpu_asic = 1'b1;
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`else
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wire cpu_asic = 1'b0;
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`endif
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wire [4:0] user_version = `USER_VERSION;
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wire [6:0] per_space = (`PER_SIZE >> 9); // cpu_id_per * 512 = peripheral space size
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`ifdef MULTIPLIER
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wire mpy_info = 1'b1;
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`else
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wire mpy_info = 1'b0;
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`endif
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wire [8:0] dmem_size = (`DMEM_SIZE >> 7); // cpu_id_dmem * 128 = data memory size
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wire [5:0] pmem_size = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size
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assign cpu_id = {pmem_size,
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dmem_size,
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mpy_info,
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per_space,
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user_version,
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cpu_asic,
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cpu_version};
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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// Data output mux
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wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1]}})} << (8 & {4{IE1[0]}});
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wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
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wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
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wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
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wire [15:0] per_dout = ie1_rd |
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ifg1_rd |
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cpu_id_lo_rd |
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cpu_id_hi_rd;
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//=============================================================================
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// 5) NMI GENERATION
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//=============================================================================
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// NOTE THAT THE NMI INPUT IS ASSUMED TO BE NON-GLITCHY
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`ifdef NMI
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//-----------------------------------
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// Edge selection
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//-----------------------------------
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wire nmi_pol = nmi ^ wdtnmies;
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//-----------------------------------
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// Pulse capture and synchronization
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//-----------------------------------
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`ifdef SYNC_NMI
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`ifdef ASIC
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// Glitch free reset for the event capture
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reg nmi_capture_rst;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) nmi_capture_rst <= 1'b1;
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else nmi_capture_rst <= ifg1_wr & ~ifg1_nxt[4];
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// NMI event capture
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wire nmi_capture;
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omsp_wakeup_cell wakeup_cell_nmi (
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.wkup_out (nmi_capture), // Wakup signal (asynchronous)
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.scan_clk (mclk), // Scan clock
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.scan_mode (scan_mode), // Scan mode
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.scan_rst (puc_rst), // Scan reset
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.wkup_clear (nmi_capture_rst), // Glitch free wakeup event clear
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.wkup_event (nmi_pol) // Glitch free asynchronous wakeup event
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);
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`else
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wire nmi_capture = nmi_pol;
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`endif
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// Synchronization
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wire nmi_s;
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omsp_sync_cell sync_cell_nmi (
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.data_out (nmi_s),
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.data_in (nmi_capture),
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.clk (mclk),
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.rst (puc_rst)
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);
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`else
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wire nmi_capture = nmi_pol;
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wire nmi_s = nmi_pol;
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`endif
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//-----------------------------------
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// NMI Pending flag
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//-----------------------------------
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// Delay
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reg nmi_dly;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) nmi_dly <= 1'b0;
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else nmi_dly <= nmi_s;
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// Edge detection
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assign nmi_edge = ~nmi_dly & nmi_s;
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// NMI pending
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wire nmi_pnd = nmiifg & nmie;
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// NMI wakeup
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`ifdef ASIC
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wire nmi_wkup;
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omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
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`else
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wire nmi_wkup = 1'b0;
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`endif
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`else
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wire nmi_pnd = 1'b0;
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wire nmi_wkup = 1'b0;
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`endif
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endmodule // omsp_sfr
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_undefines.v"
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`endif
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