mirror of https://github.com/YosysHQ/yosys.git
90 lines
3.5 KiB
Verilog
90 lines
3.5 KiB
Verilog
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_and_gate.v
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//
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// *Module Description:
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// Generic AND gate cell for the openMSP430
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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module omsp_and_gate (
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// OUTPUTs
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y, // AND gate output
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// INPUTs
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a, // AND gate input A
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b // AND gate input B
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);
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// OUTPUTs
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//=========
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output y; // AND gate output
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// INPUTs
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//=========
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input a; // AND gate input A
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input b; // AND gate input B
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//=============================================================================
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// 1) SOME COMMENTS ON THIS MODULE
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//=============================================================================
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//
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// In its ASIC version, some combinatorial pathes of the openMSP430 are
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// sensitive to glitches, in particular the ones generating the wakeup
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// signals.
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// To prevent synthesis from optmizing combinatorial clouds into glitchy
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// logic, this AND gate module has been instanciated in the critical places.
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//
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// Make sure that synthesis doesn't ungroup this module. As an alternative,
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// a standard cell from the library could also be directly instanciated here
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// (don't forget the "dont_touch" attribute)
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//
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//
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//=============================================================================
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// 2) AND GATE
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//=============================================================================
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assign y = a & b;
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endmodule // omsp_and_gate
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