yosys/passes
Clifford Wolf dc30b034f7 Fixed "dff2dffe -direct-match" 2015-04-16 11:47:59 +02:00
..
abc Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
cmds Added "splice -wires" 2015-04-13 19:28:12 +02:00
equiv Replaced ezDefaultSAT with ezSatPtr 2015-02-21 12:15:41 +01:00
fsm Added onehot attribute 2015-02-04 18:52:54 +01:00
hierarchy Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
memory Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
opt Added handling of bool-output cells to "wreduce" 2015-04-13 19:27:49 +02:00
proc Minor fixes in handling of "init" attribute 2015-04-09 15:12:26 +02:00
sat Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
techmap Fixed "dff2dffe -direct-match" 2015-04-16 11:47:59 +02:00
tests Replaced ezDefaultSAT with ezSatPtr 2015-02-21 12:15:41 +01:00