yosys/techlibs/common
Clifford Wolf 95944eb69e make all vector-size related integer params in $mem sim model signed
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
2015-04-05 17:26:53 +02:00
..
Makefile.inc Added cells.lib 2015-01-16 15:50:42 +01:00
adff2dff.v Added adff2dff.v (for techmap -share_map) 2014-08-07 16:14:38 +02:00
blackbox.sed Fixes and cleanups for blackbox.v 2014-09-08 13:31:04 +02:00
cells.lib Added cells.lib 2015-01-16 15:50:42 +01:00
pmux2mux.v Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
simcells.v Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
simlib.v make all vector-size related integer params in $mem sim model signed 2015-04-05 17:26:53 +02:00
synth.cc Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
techmap.v Improvements in simplemap api, added $ne $nex $eq $eqx support 2014-12-24 10:49:24 +01:00