yosys/passes
Clifford Wolf 2d98db73e3 Rename opt_lut.cpp to opt_lut.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-05 18:03:58 +01:00
..
cmds Merge pull request #625 from aman-goel/master 2018-09-14 12:36:13 +02:00
equiv using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal 2018-10-21 11:32:44 -07:00
fsm Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
hierarchy Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
memory memory_bram: Reset make_outreg when growing read ports 2018-10-19 14:46:31 +01:00
opt Rename opt_lut.cpp to opt_lut.cc 2018-12-05 18:03:58 +01:00
proc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
sat Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
techmap Fix typo 2018-12-04 23:30:23 +01:00
tests Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00