mirror of https://github.com/YosysHQ/yosys.git
73 lines
2.4 KiB
C++
73 lines
2.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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struct ScatterPass : public Pass {
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ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" scatter [selection]\n");
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log("\n");
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log("This command adds additional intermediate nets on all cell ports. This is used\n");
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log("for testing the correct use of the SigMap helper in passes. If you don't know\n");
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log("what this means: don't worry -- you only need this pass when testing your own\n");
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log("extensions to Yosys.\n");
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log("\n");
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log("Use the opt_clean command to get rid of the additional nets.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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CellTypes ct(design);
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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{
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if (!design->selected(mod_it.second))
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continue;
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for (auto &c : mod_it.second->cells)
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for (auto &p : c.second->connections)
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{
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = NEW_ID;
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wire->width = p.second.width;
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mod_it.second->add(wire);
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if (ct.cell_output(c.second->type, p.first)) {
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RTLIL::SigSig sigsig(p.second, wire);
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mod_it.second->connections.push_back(sigsig);
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} else {
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RTLIL::SigSig sigsig(wire, p.second);
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mod_it.second->connections.push_back(sigsig);
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}
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p.second = wire;
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}
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}
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}
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} ScatterPass;
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