yosys/tests/arch
Marcelina Kościelnicka 18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg.
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
2021-05-25 22:42:03 +02:00
..
anlogic memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
common intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
ecp5 memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
efinix tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
gowin tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
ice40 tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
intel_alm memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
machxo2 machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
nexus memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
quicklogic quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
xilinx ast: Use better parameter serialization for paramod names. 2021-03-18 00:52:00 +01:00
run-test.sh Add default assignments to SB_LUT4 2021-04-20 12:46:21 +02:00