yosys/passes
Clifford Wolf 28cf48e31f Some improvements in FSM mapping and recoding 2014-08-14 11:22:45 +02:00
..
abc Added "abc -D" for setting delay target 2014-08-14 11:05:25 +02:00
cmds Fixed build with gcc-4.6 2014-08-07 22:37:01 +02:00
fsm Some improvements in FSM mapping and recoding 2014-08-14 11:22:45 +02:00
hierarchy More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
memory Various improvements in memory_dff pass 2014-08-06 14:31:38 +02:00
opt Fixed a performance bug in opt_reduce 2014-08-02 15:12:16 +02:00
proc Fixed handling of constant-true branches in proc_clean 2014-08-12 17:35:22 +02:00
sat Fixed "share" for complex scenarios with never-active cells 2014-08-09 17:07:20 +02:00
techmap Implemented recursive techmap 2014-08-03 12:40:43 +02:00
tests More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00