Clifford Wolf 27a872d1e7 Added support for "upto" wires to Verilog front- and back-end		2014-07-28 14:25:03 +02:00
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asicworld	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
hana	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
memories	Added SAT-based write-port sharing to memory_share	2014-07-19 15:33:55 +02:00
realmath	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
sat	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
share	Wider range of cell types supported in "share" pass	2014-07-21 12:18:29 +02:00
simple	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
techmap	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	2014-07-16 14:08:51 +02:00
tools	Added "opt_const -fine" and "opt_reduce -fine"	2014-07-21 16:34:16 +02:00
various	Added tests/various/.gitignore	2014-07-26 17:43:41 +02:00
vloghtb	Improvements in tests/vloghtb	2014-07-28 09:15:40 +02:00