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18 lines
738 B
Plaintext
18 lines
738 B
Plaintext
read_verilog alu.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 66 t:AL_MAP_ADDER
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select -assert-count 32 t:AL_MAP_LUT1
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select -assert-count 23 t:AL_MAP_LUT2
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select -assert-count 61 t:AL_MAP_LUT3
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select -assert-count 209 t:AL_MAP_LUT4
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select -assert-count 100 t:AL_MAP_LUT5
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select -assert-count 79 t:AL_MAP_LUT6
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select -assert-count 32 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
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