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yosys/tests/anlogic
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SergeyDegtyar 27377c4663 Add new tests for Anlogic architecture 
Problems/questions:
	- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
		Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
	- Internal cell type $_TBUF_  is present.
 		2019-09-23 12:12:02 +03:00
..
.gitignore Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
add_sub.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
add_sub.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
alu.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
alu.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
counter.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
counter.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
dffs.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
dffs.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
fsm.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
fsm.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
latches.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
latches.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
memory.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
memory.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
mux.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
mux.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
run-test.sh Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
shifter.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
shifter.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
tribuf.v Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00
tribuf.ys Add new tests for Anlogic architecture 2019-09-23 12:12:02 +03:00