yosys/techlibs/common
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
..
.gitignore Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Makefile.inc Added "prep" command 2015-10-14 22:46:41 +02:00
adff2dff.v Added adff2dff.v (for techmap -share_map) 2014-08-07 16:14:38 +02:00
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib Added cells.lib 2015-01-16 15:50:42 +01:00
pmux2mux.v Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
prep.cc Added "prep -nokeepdc" 2016-09-30 17:02:52 +02:00
simcells.v Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
simlib.v Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
synth.cc Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
techmap.v Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00