Jannis Harder 94d7c22714 yosys-witness: Add aiw2yw --present-only to omit unused signals		2023-12-14 16:45:19 +01:00
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aiger	Merge pull request #3778 from jix/yw_clk2fflogic	2023-06-05 16:15:04 +02:00
blif	Slightly adjust the wording of "write_blif" help	2023-07-10 12:41:43 +02:00
btor	Use clk2fflogic attr on cells to track original FF names in witnesses	2023-05-25 12:48:02 +02:00
cxxrtl	cxxrtl: Mask `bmux` result appropriately	2023-12-14 06:57:28 +00:00
edif	Improve EDIF lib_cell_ports scan	2023-06-20 10:42:05 +02:00
firrtl	Mention 'bwmuxmap' in 'write_firrtl' help	2023-07-10 12:45:03 +02:00
intersynth	…
jny	Drop stray 'cellaigs.h' include from backend passes	2023-07-10 12:45:03 +02:00
json	…
rtlil	backends/rtlil: Do not shorten a value with z bits to 'x	2023-01-29 14:02:25 +01:00
simplec	…
smt2	yosys-witness: Add aiw2yw --present-only to omit unused signals	2023-12-14 16:45:19 +01:00
smv	…
spice	…
table	…
verilog	write_verilog: avoid emitting empty cases.	2023-10-08 01:11:30 +02:00