yosys/passes
Krystine Sherwin 7ea06990e7
Refactor full_selection
The `Design::selected_*()` methods no longer unconditionally skip boxed modules.  Instead, selections are now box and design aware.
The selection constructor now optionally takes a design pointer, and has a new `selects_boxes` flag.  If the selection has an assigned design, then `Selection::selected_*()` will only return true for boxed modules if the selects_boxes flag is set.  A warning is raised if a selection is checked and no design is set.  Selections can change design via the `Selection::optimize()` method.
Most places that iterate over `Design::modules()` and check `Selection::selected_module()` should instead use `Design::selected_modules()`.
Since boxed modules should only ever be selected explicitly, and `full_selection` (now) refers to all non-boxed modules, `Selection::optimize()` will clear the `full_selection` flag if the `selects_boxes` flag is enabled, and instead explicitly selects all modules (including boxed modules).  This also means that `full_selection` will only get automatically applied to a design without any boxed modules.

These changes necessitated a number of changes to `select.cc` in order to support this functionality when operating on selections, in particular when combining selections (e.g. by union or difference).
To minimize redundancy, a number of places that previously iterated over `design->modules()` now push the current selection to the design, use `design->selected_modules()`, and then pop the selection when done.

Introduce `RTLIL::NamedObject`, to allow for iterating over all members of a module with a single iterator instead of needing to iterate over wires, cells, memories, and processes separately.
Also implement `Module::selected_{memories, processes, members}()` to match wires and cells methods.  The `selected_members()` method combines each of the other `selected_*()` methods into a single list.
2024-11-19 08:44:45 +13:00
..
cmds Refactor full_selection 2024-11-19 08:44:45 +13:00
equiv equiv_simple: Take FFs into account for driver map 2024-02-21 12:05:52 +01:00
fsm rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
hierarchy rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
memory rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
opt rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
pmgen Merge pull request #4525 from georgerennie/peepopt_clock_gate 2024-11-11 14:49:09 +01:00
proc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
sat Merge pull request #4525 from georgerennie/peepopt_clock_gate 2024-11-11 14:49:09 +01:00
techmap dfflibmap: move expression code into libparse 2024-11-13 16:06:57 +00:00
tests rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00