yosys/passes
Clifford Wolf 25844b5683 Fixed "abc" pass for clk and enable signals driven by logic 2014-12-21 11:13:25 +01:00
..
abc Fixed "abc" pass for clk and enable signals driven by logic 2014-12-21 11:13:25 +01:00
cmds Introducing YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN 2014-11-09 10:55:04 +01:00
fsm Added log_warning() API 2014-11-09 10:44:23 +01:00
hierarchy Checking existence of ports in "hierarchy -check" 2014-12-19 18:47:19 +01:00
memory Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
opt Improved TopoSort determinism 2014-11-07 15:21:03 +01:00
proc Added log_warning() API 2014-11-09 10:44:23 +01:00
sat Added log_warning() API 2014-11-09 10:44:23 +01:00
techmap Added functionality to dff2dffe pass 2014-12-08 15:38:58 +01:00
tests Fixed typo in test_cell 2014-10-18 16:52:06 +01:00