.. |
tests
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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2019-08-12 12:06:45 -07:00 |
.gitignore
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Initialization support for all iCE40 bram modes
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2015-04-26 08:39:31 +02:00 |
Makefile.inc
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Makefile: don't assume python is called `python3`
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2019-10-19 14:04:52 +08:00 |
abc9_hx.box
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Cleanup ice40 boxes
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2019-12-31 18:29:37 -08:00 |
abc9_hx.lut
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
abc9_lp.box
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Cleanup ice40 boxes
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2019-12-31 18:29:37 -08:00 |
abc9_lp.lut
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
abc9_model.v
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-24 11:59:48 -08:00 |
abc9_u.box
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-24 11:59:48 -08:00 |
abc9_u.lut
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
arith_map.v
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-24 11:59:48 -08:00 |
brams.txt
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
brams_init.py
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Switched to Python 3
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2015-08-22 09:59:33 +02:00 |
brams_map.v
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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2019-02-28 16:23:40 -08:00 |
cells_map.v
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xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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2020-01-27 13:30:27 -08:00 |
cells_sim.v
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ice40: add SB_SPRAM256KA arrival time
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2020-01-24 12:17:09 -08:00 |
dsp_map.v
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Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
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2019-08-08 12:56:05 -07:00 |
ice40_braminit.cc
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substr() -> compare()
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2019-08-07 12:20:08 -07:00 |
ice40_ffinit.cc
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ice40: Demote conflicting FF init values to a warning
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2019-12-31 02:38:10 +01:00 |
ice40_ffssr.cc
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ice40: Honor the "dont_touch" attribute in FFSSR pass
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2018-12-08 22:46:28 +01:00 |
ice40_opt.cc
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Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
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2020-01-27 14:02:13 -08:00 |
latches_map.v
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Added synth_ice40 support for latches via logic loops
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2016-05-06 23:02:37 +02:00 |
synth_ice40.cc
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synth_ice40: call wreduce before mul2dsp
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2020-01-17 15:41:55 -08:00 |