This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
22a998903b
yosys
/
passes
History
Clifford Wolf
22a998903b
Added %D and %c select commands
2014-06-14 16:19:32 +02:00
..
abc
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
2014-03-12 23:17:14 +01:00
cmds
Added %D and %c select commands
2014-06-14 16:19:32 +02:00
fsm
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
2014-03-11 14:24:24 +01:00
hierarchy
fixed cell array handling of positional arguments
2014-06-07 12:17:11 +02:00
memory
Fixed log messages in memory_dff
2014-06-01 11:32:27 +02:00
opt
Fixed bug in opt_reduce (see vloghammer issue_044)
2014-05-12 12:45:47 +02:00
proc
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
2014-02-21 23:34:45 +01:00
sat
added log_header to miter and expose pass, show cell type for exposed ports
2014-05-28 18:05:38 +02:00
techmap
be more verbose when techmap yielded processes
2014-05-26 17:13:41 +02:00