yosys/backends
whitequark 86f2804dc3 write_verilog: dump zero width sigspecs correctly.
Before this commit, zero width sigspecs were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

PR #1203 has addressed this issue before, but in an incomplete way.
2021-12-11 12:01:52 +00:00
..
aiger sta: very crude static timing analysis pass 2021-11-25 17:20:27 +01:00
blif Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
btor Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
cxxrtl Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
edif Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
firrtl Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
intersynth Intersynth URL 2021-06-09 12:42:52 +02:00
json Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
protobuf Fix protobuf backend build dependencies 2021-09-17 13:36:39 +10:00
rtlil Add optimization to rtlil back-end for all-x parameter values 2021-09-27 16:02:20 +02:00
simplec Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
smt2 Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
smv Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
spice Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
table Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
verilog write_verilog: dump zero width sigspecs correctly. 2021-12-11 12:01:52 +00:00