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Clifford Wolf 019b301541 Early wire/reg/parameter width calculation in ast/simplify 2013-11-24 19:40:23 +01:00
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ast Early wire/reg/parameter width calculation in ast/simplify 2013-11-24 19:40:23 +01:00
ilang Added support for signed parameters in ilang 2013-11-24 17:37:27 +01:00
verilog Improved handling of initialized registers 2013-11-23 16:26:59 +01:00