yosys/frontends/verilog
Clifford Wolf 0c4c79c4c6 Fixed parsing of TOK_INTEGER (implies TOK_SIGNED) 2014-06-16 15:02:40 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
const2ast.cc Improved parsing of large integer constants 2014-06-15 08:48:17 +02:00
lexer.l Added handling of real-valued parameters/localparams 2014-06-14 12:00:47 +02:00
parser.y Fixed parsing of TOK_INTEGER (implies TOK_SIGNED) 2014-06-16 15:02:40 +02:00
preproc.cc Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
verilog_frontend.cc Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
verilog_frontend.h Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00