yosys/frontends
Clifford Wolf b171a4c1bc Added "inout" ports support to read_liberty 2014-07-16 18:12:46 +02:00
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ast changes in verilog frontend for new $mem/$memwr WR_EN interface 2014-07-16 12:49:50 +02:00
ilang Fixed clang -Wdeprecated-register warnings 2014-04-20 14:28:23 +02:00
liberty Added "inout" ports support to read_liberty 2014-07-16 18:12:46 +02:00
verific Fixed mapping of Verific WIDE_DFFRS operator 2014-03-20 13:40:01 +01:00
verilog fixed parsing of constant with comment between size and value 2014-07-02 06:27:04 +02:00
vhdl2verilog Added passing of various options to vhdl2verilog 2014-07-12 10:02:39 +02:00