Zachary Snow 220cb1f7bb verilog: error on macro invocations with missing argument lists ... This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.		2021-02-19 09:18:41 -05:00
..
.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
Makefile.inc	Treat all bison warnings as errors in verilog front-end	2020-07-15 11:57:31 +02:00
const2ast.cc	Replacing log_error for log_file_error due consistency	2020-03-31 12:01:29 -06:00
preproc.cc	verilog: error on macro invocations with missing argument lists	2021-02-19 09:18:41 -05:00
preproc.h	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
verilog_frontend.cc	Fix SYNTHESIS always being defined in Verilog frontend	2020-12-01 01:37:19 +00:00
verilog_frontend.h	frontend: cleanup to use more ID::*, more dict<> instead of map<>	2020-05-04 10:48:37 -07:00
verilog_lexer.l	Merge pull request #2179 from splhack/static-cast	2020-07-01 16:40:20 +02:00
verilog_parser.y	Merge pull request #2578 from zachjs/genblk-port	2021-02-11 10:26:49 -05:00