Clifford Wolf 19a980277f Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr		2017-01-31 15:54:41 +01:00
..
cmds	Added "check -initdrv"	2017-01-04 18:12:41 +01:00
equiv	Add $ff and $_FF_ support to equiv_simple	2017-01-30 10:50:38 +01:00
fsm	Be more conservative with merging large cells into FSMs	2017-01-26 09:19:28 +01:00
hierarchy	passes/hierarchy: delete some dead code	2017-01-15 16:39:12 -06:00
memory	Typo fix.	2016-09-08 10:57:16 +03:00
opt	Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr	2017-01-31 15:54:41 +01:00
proc	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
sat	Bugfix in "miter -assert" handling of assumptions	2016-10-17 14:56:58 +02:00
techmap	Improved ABC default scripts	2016-11-19 18:20:54 +01:00
tests	Cosmetic fix in test_autotb.cc	2016-09-19 20:43:43 +02:00