yosys/tests/svtypes
Dag Lem fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv 2023-05-04 14:28:21 +02:00
..
.gitignore Cleaner tests for RTLIL cells in struct_dynamic_range.sv 2023-05-04 14:28:21 +02:00
enum_simple.sv Revert typedef tests to standard grammar. 2020-03-22 18:20:46 -07:00
enum_simple.ys simple enum test 2020-01-16 18:09:03 -05:00
logic_rom.sv ast/simplify: don't bitblast async ROMs declared as `logic`. 2020-05-05 04:16:59 +00:00
logic_rom.ys Add v2 memory cells. 2021-08-11 13:34:10 +02:00
multirange_array.sv Test multirange (unpacked) arrays size 2020-08-03 15:34:55 +02:00
multirange_subarray_access.ys Add test for subarray access on multidimensional arrays 2020-08-03 17:07:33 +02:00
run-test.sh tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
static_cast_negative.ys static cast: add tests 2020-06-19 17:40:38 -07:00
static_cast_nonconst.ys static cast: add tests 2020-06-19 17:40:38 -07:00
static_cast_simple.sv static cast: add tests 2020-06-19 17:40:38 -07:00
static_cast_verilog.ys static cast: add tests 2020-06-19 17:40:38 -07:00
static_cast_zero.ys static cast: add tests 2020-06-19 17:40:38 -07:00
struct_array.sv Index struct/union members within corresponding wire chunks 2023-03-05 14:54:17 +01:00
struct_dynamic_range.sv Handling of attributes for struct / union variables 2023-05-03 18:44:07 +02:00
struct_dynamic_range.ys Cleaner tests for RTLIL cells in struct_dynamic_range.sv 2023-05-04 14:28:21 +02:00
struct_simple.sv Allow structs within structs. 2020-05-12 17:20:34 +01:00
struct_sizebits.sv Corrected tests for data and array queries on struct/union item expressions 2023-02-15 12:36:29 +01:00
typedef_initial_and_assign.sv sv: improve support for wire and var with user-defined types 2021-08-12 22:41:41 -06:00
typedef_initial_and_assign.ys sv: improve support for wire and var with user-defined types 2021-08-12 22:41:41 -06:00
typedef_memory.sv Revert typedef tests to standard grammar. 2020-03-22 18:20:46 -07:00
typedef_memory.ys Add v2 memory cells. 2021-08-11 13:34:10 +02:00
typedef_memory_2.sv Revert typedef tests to standard grammar. 2020-03-22 18:20:46 -07:00
typedef_memory_2.ys Add v2 memory cells. 2021-08-11 13:34:10 +02:00
typedef_package.sv support using previously declared types/localparams/params in package 2020-04-07 00:38:15 -04:00
typedef_param.sv Revert typedef tests to standard grammar. 2020-03-22 18:20:46 -07:00
typedef_scopes.sv verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
typedef_simple.sv Revert typedef tests to standard grammar. 2020-03-22 18:20:46 -07:00
typedef_struct.sv Resolve struct member package types 2023-01-29 13:51:44 -05:00
typedef_struct_port.sv Add typedef input/output test 2021-01-18 17:31:22 +01:00
typedef_struct_port.ys Add typedef input/output test 2021-01-18 17:31:22 +01:00
union_simple.sv Handle struct members of union type (#3641) 2023-01-29 13:45:45 -05:00