mirror of https://github.com/YosysHQ/yosys.git
368 lines
12 KiB
C++
368 lines
12 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivStructWorker
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{
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Module *module;
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SigMap sigmap;
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SigMap equiv_bits;
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bool mode_fwd;
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bool mode_icells;
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int merge_count;
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const pool<IdString> &fwonly_cells;
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struct merge_key_t
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{
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IdString type;
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vector<pair<IdString, Const>> parameters;
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vector<pair<IdString, int>> port_sizes;
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vector<tuple<IdString, int, SigBit>> connections;
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bool operator==(const merge_key_t &other) const {
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return type == other.type && connections == other.connections &&
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parameters == other.parameters && port_sizes == other.port_sizes;
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}
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unsigned int hash() const {
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unsigned int h = mkhash_init;
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h = mkhash(h, mkhash(type));
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h = mkhash(h, mkhash(parameters));
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h = mkhash(h, mkhash(connections));
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return h;
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}
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};
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dict<merge_key_t, pool<IdString>> merge_cache;
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pool<merge_key_t> fwd_merge_cache, bwd_merge_cache;
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void merge_cell_pair(Cell *cell_a, Cell *cell_b)
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{
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SigMap merged_map;
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merge_count++;
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SigSpec inputs_a, inputs_b;
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vector<string> input_names;
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for (auto &port_a : cell_a->connections())
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{
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SigSpec bits_a = sigmap(port_a.second);
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SigSpec bits_b = sigmap(cell_b->getPort(port_a.first));
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log_assert(GetSize(bits_a) == GetSize(bits_b));
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if (!cell_a->output(port_a.first))
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for (int i = 0; i < GetSize(bits_a); i++)
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if (bits_a[i] != bits_b[i]) {
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inputs_a.append(bits_a[i]);
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inputs_b.append(bits_b[i]);
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input_names.push_back(GetSize(bits_a) == 1 ? port_a.first.str() :
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stringf("%s[%d]", log_id(port_a.first), i));
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}
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}
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for (int i = 0; i < GetSize(inputs_a); i++) {
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SigBit bit_a = inputs_a[i], bit_b = inputs_b[i];
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SigBit bit_y = module->addWire(NEW_ID);
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log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n",
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input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y));
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module->addEquiv(NEW_ID, bit_a, bit_b, bit_y);
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merged_map.add(bit_a, bit_y);
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merged_map.add(bit_b, bit_y);
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}
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std::vector<IdString> outport_names, inport_names;
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for (auto &port_a : cell_a->connections())
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if (cell_a->output(port_a.first))
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outport_names.push_back(port_a.first);
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else
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inport_names.push_back(port_a.first);
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for (auto &pn : inport_names)
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cell_a->setPort(pn, merged_map(sigmap(cell_a->getPort(pn))));
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for (auto &pn : outport_names) {
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SigSpec sig_a = cell_a->getPort(pn);
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SigSpec sig_b = cell_b->getPort(pn);
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module->connect(sig_b, sig_a);
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}
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auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged");
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merged_attr.insert(log_id(cell_b));
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cell_a->add_strpool_attribute("\\equiv_merged", merged_attr);
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module->remove(cell_b);
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}
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EquivStructWorker(Module *module, bool mode_fwd, bool mode_icells, const pool<IdString> &fwonly_cells, int iter_num) :
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module(module), sigmap(module), equiv_bits(module),
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mode_fwd(mode_fwd), mode_icells(mode_icells), merge_count(0), fwonly_cells(fwonly_cells)
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{
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log(" Starting iteration %d.\n", iter_num);
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pool<SigBit> equiv_inputs;
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pool<IdString> cells;
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv") {
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SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
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SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
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equiv_bits.add(sig_b, sig_a);
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equiv_inputs.insert(sig_a);
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equiv_inputs.insert(sig_b);
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cells.insert(cell->name);
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} else {
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if (mode_icells || module->design->module(cell->type))
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cells.insert(cell->name);
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}
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv") {
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SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
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SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
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SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
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if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
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log(" Purging redundant $equiv cell %s.\n", log_id(cell));
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module->connect(sig_y, sig_a);
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module->remove(cell);
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merge_count++;
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}
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}
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if (merge_count > 0)
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return;
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for (auto cell_name : cells)
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{
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merge_key_t key;
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vector<tuple<IdString, int, SigBit>> fwd_connections;
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Cell *cell = module->cell(cell_name);
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key.type = cell->type;
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for (auto &it : cell->parameters)
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key.parameters.push_back(it);
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std::sort(key.parameters.begin(), key.parameters.end());
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for (auto &it : cell->connections())
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key.port_sizes.push_back(make_pair(it.first, GetSize(it.second)));
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std::sort(key.port_sizes.begin(), key.port_sizes.end());
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for (auto &conn : cell->connections())
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{
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if (cell->input(conn.first)) {
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SigSpec sig = sigmap(conn.second);
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for (int i = 0; i < GetSize(sig); i++)
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fwd_connections.push_back(make_tuple(conn.first, i, sig[i]));
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}
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if (cell->output(conn.first)) {
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SigSpec sig = equiv_bits(conn.second);
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for (int i = 0; i < GetSize(sig); i++) {
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key.connections.clear();
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key.connections.push_back(make_tuple(conn.first, i, sig[i]));
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if (merge_cache.count(key))
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bwd_merge_cache.insert(key);
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merge_cache[key].insert(cell_name);
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}
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}
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}
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std::sort(fwd_connections.begin(), fwd_connections.end());
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key.connections.swap(fwd_connections);
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if (merge_cache.count(key))
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fwd_merge_cache.insert(key);
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merge_cache[key].insert(cell_name);
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}
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for (int phase = 0; phase < 2; phase++)
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{
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auto &queue = phase ? bwd_merge_cache : fwd_merge_cache;
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for (auto &key : queue)
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{
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const char *strategy = nullptr;
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vector<Cell*> gold_cells, gate_cells, other_cells;
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vector<pair<Cell*, Cell*>> cell_pairs;
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IdString cells_type;
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for (auto cell_name : merge_cache[key]) {
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Cell *c = module->cell(cell_name);
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if (c != nullptr) {
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string n = cell_name.str();
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cells_type = c->type;
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if (GetSize(n) > 5 && n.substr(GetSize(n)-5) == "_gold")
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gold_cells.push_back(c);
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else if (GetSize(n) > 5 && n.substr(GetSize(n)-5) == "_gate")
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gate_cells.push_back(c);
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else
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other_cells.push_back(c);
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}
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}
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if (phase && fwonly_cells.count(cells_type))
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continue;
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if (GetSize(gold_cells) > 1 || GetSize(gate_cells) > 1 || GetSize(other_cells) > 1)
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{
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strategy = "deduplicate";
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for (int i = 0; i+1 < GetSize(gold_cells); i += 2)
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cell_pairs.push_back(make_pair(gold_cells[i], gold_cells[i+1]));
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for (int i = 0; i+1 < GetSize(gate_cells); i += 2)
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cell_pairs.push_back(make_pair(gate_cells[i], gate_cells[i+1]));
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for (int i = 0; i+1 < GetSize(other_cells); i += 2)
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cell_pairs.push_back(make_pair(other_cells[i], other_cells[i+1]));
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goto run_strategy;
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}
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if (GetSize(gold_cells) == 1 && GetSize(gate_cells) == 1)
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{
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strategy = "gold-gate-pairs";
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cell_pairs.push_back(make_pair(gold_cells[0], gate_cells[0]));
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goto run_strategy;
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}
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if (GetSize(gold_cells) == 1 && GetSize(other_cells) == 1)
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{
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strategy = "gold-guess";
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cell_pairs.push_back(make_pair(gold_cells[0], other_cells[0]));
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goto run_strategy;
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}
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if (GetSize(other_cells) == 1 && GetSize(gate_cells) == 1)
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{
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strategy = "gate-guess";
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cell_pairs.push_back(make_pair(other_cells[0], gate_cells[0]));
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goto run_strategy;
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}
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log_assert(GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells) < 2);
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continue;
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run_strategy:
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int total_group_size = GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells);
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log(" %s merging %d %s cells (from group of %d) using strategy %s:\n", phase ? "Bwd" : "Fwd",
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2*GetSize(cell_pairs), log_id(cells_type), total_group_size, strategy);
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for (auto it : cell_pairs) {
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log(" Merging cells %s and %s.\n", log_id(it.first), log_id(it.second));
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merge_cell_pair(it.first, it.second);
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}
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}
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if (merge_count > 0)
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return;
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}
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log(" Nothing to merge.\n");
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}
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};
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struct EquivStructPass : public Pass {
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EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_struct [options] [selection]\n");
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log("\n");
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log("This command adds additional $equiv cells based on the assumption that the\n");
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log("gold and gate circuit are structurally equivalent. Note that this can introduce\n");
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log("bad $equiv cells in cases where the netlists are not structurally equivalent,\n");
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log("for example when analyzing circuits with cells with commutative inputs. This\n");
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log("command will also de-duplicate gates.\n");
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log("\n");
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log(" -fwd\n");
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log(" by default this command performans forward sweeps until nothing can\n");
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log(" be merged by forwards sweeps, then backward sweeps until forward\n");
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log(" sweeps are effective again. with this option set only forward sweeps\n");
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log(" are performed.\n");
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log("\n");
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log(" -fwonly <cell_type>\n");
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log(" add the specified cell type to the list of cell types that are only\n");
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log(" merged in forward sweeps and never in backward sweeps. $equiv is in\n");
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log(" this list automatically.\n");
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log("\n");
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log(" -icells\n");
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log(" by default, the internal RTL and gate cell types are ignored. add\n");
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log(" this option to also process those cell types with this command.\n");
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log("\n");
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log(" -maxiter <N>\n");
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log(" maximum number of iterations to run before aborting\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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pool<IdString> fwonly_cells({ "$equiv" });
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bool mode_icells = false;
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bool mode_fwd = false;
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int max_iter = -1;
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log_header("Executing EQUIV_STRUCT pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-fwd") {
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mode_fwd = true;
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continue;
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}
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if (args[argidx] == "-icells") {
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mode_icells = true;
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continue;
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}
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if (args[argidx] == "-fwonly" && argidx+1 < args.size()) {
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fwonly_cells.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-maxiter" && argidx+1 < args.size()) {
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max_iter = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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int module_merge_count = 0;
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log("Running equiv_struct on module %s:\n", log_id(module));
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for (int iter = 0;; iter++) {
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if (iter == max_iter) {
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log(" Reached iteration limit of %d.\n", iter);
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break;
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}
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EquivStructWorker worker(module, mode_fwd, mode_icells, fwonly_cells, iter+1);
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if (worker.merge_count == 0)
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break;
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module_merge_count += worker.merge_count;
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}
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if (module_merge_count)
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log(" Performed a total of %d merges in module %s.\n", module_merge_count, log_id(module));
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}
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}
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} EquivStructPass;
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PRIVATE_NAMESPACE_END
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