Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping		2016-02-01 12:40:32 +01:00
..
cmds	Fixed "splitnets -ports" for hierarchical designs	2015-12-22 13:25:00 +01:00
equiv	Added "equiv_struct -fwonly"	2016-01-08 10:59:16 +01:00
fsm	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
hierarchy	Added "submod -copy"	2016-01-08 09:08:12 +01:00
memory	Bugfix in memory_dff	2015-10-31 22:01:41 +01:00
opt	Improvements in wreduce	2015-10-31 13:39:30 +01:00
proc	Improved proc_mux performance for huge always blocks	2015-12-02 22:02:20 +01:00
sat	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
techmap	Added "abc -luts" option, Improved Xilinx logic mapping	2016-02-01 12:40:32 +01:00
tests	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00