riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/frontends
History
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
..
ast SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
ilang SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
liberty SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
verific Fixed mapping of Verific WIDE_DFFRS operator 2014-03-20 13:40:01 +01:00
verilog fixed parsing of constant with comment between size and value 2014-07-02 06:27:04 +02:00
vhdl2verilog Added passing of various options to vhdl2verilog 2014-07-12 10:02:39 +02:00