Marcelina Kościelnicka 56e7791760 verilog backend: Emit a `wire` for ports as well. ... Fixes #3177.		2022-01-31 01:08:41 +01:00
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aiger	sta: very crude static timing analysis pass	2021-11-25 17:20:27 +01:00
blif	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
btor	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
cxxrtl	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
edif	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
firrtl	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
intersynth	Intersynth URL	2021-06-09 12:42:52 +02:00
json	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
protobuf	Fix protobuf backend build dependencies	2021-09-17 13:36:39 +10:00
rtlil	rtlil: Dump empty connections when whole module is selected.	2021-12-12 01:22:06 +01:00
simplec	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
smt2	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
smv	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
spice	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
table	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
verilog	verilog backend: Emit a `wire` for ports as well.	2022-01-31 01:08:41 +01:00