mirror of https://github.com/YosysHQ/yosys.git
225 lines
5.2 KiB
Plaintext
225 lines
5.2 KiB
Plaintext
read_verilog -icells <<EOF
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module test();
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`define CELL_AY(typ) \
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wire typ``_a, typ``_y; \
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$``typ typ(.A(typ``_a), .Y(typ``_y));
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`define CELL_ABY(typ) \
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wire typ``_a, typ``_b, typ``_y; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .Y(typ``_y));
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`define CELL_SABY(typ) \
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wire typ``_a, typ``_b, typ``_y, typ``_s; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .Y(typ``_y), .S(typ``_s));
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`define CELL_ABCY(typ) \
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wire typ``_a, typ``_b, typ``_c, typ``_y; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .C(typ``_c), .Y(typ``_y));
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`define CELL_ABCDY(typ) \
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wire typ``_a, typ``_b, typ``_c, typ``_d, typ``_y; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .C(typ``_c), .D(typ``_d), .Y(typ``_y));
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`CELL_AY(_BUF_)
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`CELL_AY(_NOT_)
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`CELL_ABY(_AND_)
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`CELL_ABY(_NAND_)
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`CELL_ABY(_OR_)
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`CELL_ABY(_NOR_)
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`CELL_ABY(_XOR_)
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`CELL_ABY(_XNOR_)
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`CELL_ABY(_ANDNOT_)
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`CELL_ABY(_ORNOT_)
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`CELL_SABY(_MUX_)
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`CELL_SABY(_NMUX_)
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`CELL_ABCY(_AOI3_)
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`CELL_ABCY(_OAI3_)
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`CELL_ABCDY(_AOI4_)
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`CELL_ABCDY(_OAI4_)
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endmodule
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EOF
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expose -input c:* %ci* w:* %i
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expose c:* %co* w:* %i
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copy test gold
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select test
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write_aiger2 aiger2_gates.aig
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select -clear
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delete test
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read_aiger -module_name test aiger2_gates.aig
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select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D
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miter -equiv -make_outcmp -flatten gold test miter
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sat -verify -show-ports -prove trigger 0 miter
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design -reset
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read_verilog -icells <<EOF
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module test();
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`define BIOP(name,op,w1,w2,wy) \
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wire [w1-1:0] name``_a1; \
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wire [w2-1:0] name``_b1; \
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wire [wy-1:0] name``_y1; \
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assign name``_y1 = name``_a1 op name``_b1; \
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wire signed [w1-1:0] name``_a2; \
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wire signed [w2-1:0] name``_b2; \
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wire [wy-1:0] name``_y2; \
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assign name``_y2 = name``_a2 op name``_b2;
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`define UNOP(name,op,w1) \
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wire signed [w1-1:0] name``_a1; \
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wire signed [w1-1:0] name``_y1; \
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assign name``_y1 = op name``_a1; \
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wire [w1-1:0] name``_a2; \
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wire [w1-1:0] name``_y2; \
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assign name``_y2 = op name``_a2;
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`define UNOP_REDUCE(name,op,w1) \
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wire signed [w1-1:0] name``_a1; \
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wire name``_y1; \
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assign name``_y1 = op name``_a1; \
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wire [w1-1:0] name``_a2; \
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wire name``_y2; \
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assign name``_y2 = op name``_a2;
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`BIOP(and, &, 3, 4, 5)
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`BIOP(or, |, 4, 3, 2)
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`BIOP(xor, ^, 3, 3, 3)
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`BIOP(xnor, ~^, 3, 3, 3)
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`BIOP(logic_and, &&, 4, 3, 1)
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`BIOP(logic_or, ||, 3, 3, 2)
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`BIOP(eq, ==, 3, 3, 1)
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`BIOP(ne, !=, 3, 3, 1)
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`BIOP(lt, <, 3, 3, 1)
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`BIOP(le, <=, 3, 3, 1)
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`BIOP(gt, >, 3, 3, 1)
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`BIOP(ge, >=, 3, 3, 1)
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`UNOP(not, ~, 3)
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`UNOP_REDUCE(logic_not, !, 3)
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`UNOP_REDUCE(reduce_and, &, 3)
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`UNOP_REDUCE(reduce_or, |, 3)
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`UNOP_REDUCE(reduce_xor, ^, 3)
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`UNOP_REDUCE(reduce_xnor, ~^, 3)
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wire [3:0] mux_a, mux_b, mux_s, mux_y;
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assign mux_y = mux_s ? mux_b : mux_a;
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wire [1:0] fa_a, fa_b, fa_c, fa_x, fa_y;
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\$fa #(
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.WIDTH(2)
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) fa(.A(fa_a), .B(fa_b), .C(fa_c), .X(fa_x), .Y(fa_y));
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wire [1:0] bwmux_a, bwmux_b, bwmux_s, bwmux_y;
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\$bwmux #(
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.WIDTH(2)
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) bwmux(.A(bwmux_a), .B(bwmux_b), .S(bwmux_s), .Y(bwmux_y));
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endmodule
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EOF
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expose -input c:* %ci* w:* %i
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expose c:* %co* w:* %i
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splitnets -ports
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copy test gold
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select test
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write_aiger2 aiger2_ops.aig
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select -clear
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delete test
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read_aiger -module_name test aiger2_ops.aig
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select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D
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miter -equiv -make_outcmp -flatten gold test miter
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sat -verify -show-ports -prove trigger 0 miter
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design -reset
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read_verilog -icells <<EOF
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module submodule1(a, y1, y2);
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input wire [2:0] a;
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output wire [2:0] y1 = a + 1;
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output wire [2:0] y2 = a + 2;
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endmodule
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module submodule2(a, y1);
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input wire [2:0] a;
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output wire [2:0] y1 = ~a;
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endmodule
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module test(a, y1, y2);
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input wire [2:0] a;
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output wire [2:0] y1;
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output wire [2:0] y2;
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wire [2:0] m1;
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wire [2:0] m2;
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submodule2 s1(.a(a), .y1(m1));
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submodule1 s2(.a(m1), .y1(y1), .y2(m2));
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submodule2 s3(.a(m2), .y1(y2));
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endmodule
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EOF
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expose -input c:* %ci* w:* %i
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expose c:* %co* w:* %i
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splitnets -ports
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copy test gold
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flatten gold
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techmap submodule1
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select test
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write_aiger2 -flatten aiger2_ops.aig
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select -clear
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delete test
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read_aiger -module_name test aiger2_ops.aig
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select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D
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miter -equiv -flatten gold test miter
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sat -verify -prove trigger 0 miter
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design -reset
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read_verilog -icells <<EOF
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module test();
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wire [1:0] pmux_a, pmux_s, pmux_y;
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wire [3:0] pmux_b;
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\$pmux #(
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.S_WIDTH(2),
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.WIDTH(2)
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) pmux(.A(pmux_a), .B(pmux_b), .S(pmux_s), .Y(pmux_y));
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endmodule
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EOF
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expose -input c:* %ci* w:* %i
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expose c:* %co* w:* %i
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splitnets -ports
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opt_clean
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copy test gold
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select test
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write_aiger2 aiger2_xmodel.aig
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select -clear
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delete test
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read_aiger -module_name test aiger2_xmodel.aig
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select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D
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equiv_make gold test equiv
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equiv_induct -undef equiv
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equiv_status -assert equiv
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design -reset
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read_verilog -icells <<EOF
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module sm2(input wire [1:0] a, output wire [1:0] y);
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assign y = a + 1;
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endmodule
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module sm1(input wire [2:0] a, output wire [2:0] y);
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sm2 inst(a[1:0], y[2:1]);
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assign y[0] = !a[2];
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endmodule
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module top(input wire [4:0] a, output wire [4:0] y);
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sm1 i1(.a(a[2:0]), .y(y[2:0]));
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sm2 i2(.a(a[4:3]), .y(y[4:3]));
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endmodule
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EOF
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prep -top top
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# deal with arithmetic which is unsupported inside aiger2
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techmap t:$add
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splitnets -ports top
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write_aiger2 -flatten aiger2_flatten.aig
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flatten
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rename top gold
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read_aiger -module_name gate aiger2_flatten.aig
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miter -equiv -flatten gold gate miter
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sat -verify -prove trigger 0 miter
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