mirror of https://github.com/YosysHQ/yosys.git
27 lines
617 B
Systemverilog
27 lines
617 B
Systemverilog
// An example showing how parameters get inferred when binding
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module foo (input logic a, input logic b, output logic c);
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parameter doit = 1;
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// Magic happens here...
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endmodule
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module bar (input a, input b, output c);
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parameter doit = 1;
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assign c = doit ? a ^ b : 0;
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endmodule
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module top (input u0, input v0, output w0,
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input u1, input v1, output w1);
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foo #(.doit (0)) foo0 (.a (u0), .b (v0), .c (w0));
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foo #(.doit (1)) foo1 (.a (u1), .b (v1), .c (w1));
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bind foo bar #(.doit (doit)) bound_i (.*);
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always_comb begin
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assert (w0 == '0);
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assert (w1 == u1 ^ v1);
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end
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endmodule
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