mirror of https://github.com/YosysHQ/yosys.git
27 lines
659 B
Systemverilog
27 lines
659 B
Systemverilog
// An example of specifying multiple bind instances in a single directive. This
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// also uses explicit bound names.
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module foo (input logic a0, input logic b0, output logic c0,
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input logic a1, input logic b1, output logic c1);
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// Magic happens here...
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endmodule
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module bar (input a, input b, output c);
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assign c = a ^ b;
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endmodule
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module top ();
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logic u0, v0, w0;
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logic u1, v1, w1;
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foo foo0 (.a0 (u0), .b0 (v0), .c0 (w0),
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.a1 (u1), .b1 (v1), .c1 (w1));
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bind foo bar bar0 (.a(a0), .b(b0), .c(c0)), bar1 (.a(a1), .b(b1), .c(c1));
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always_comb begin
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assert(w0 == u0 ^ v0);
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assert(w1 == u1 ^ v1);
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end
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endmodule
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