yosys/techlibs/common
Eddie Hung 627a62a797 Make doc consistent 2019-06-14 10:32:46 -07:00
..
.gitignore
Makefile.inc
adff2dff.v
cellhelp.py
cells.lib
cmp2lut.v
dff2ff.v
gate2lut.v
pmux2mux.v
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v
simlib.v Improve $specrule interface 2019-04-23 22:57:10 +02:00
synth.cc Make doc consistent 2019-06-14 10:32:46 -07:00
techmap.v