yosys/frontends
Eddie Hung 34ae29295d read_verilog -defer should still populate module attributes 2019-08-28 19:59:09 -07:00
..
aiger Fix typo 2019-08-19 10:42:00 -07:00
ast read_verilog -defer should still populate module attributes 2019-08-28 19:59:09 -07:00
blif Change signature of parse_blif to take IdString 2019-08-15 10:26:24 -07:00
ilang Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty stoi -> atoi 2019-08-07 11:09:17 -07:00
verific Fix erroneous ifndef-NDEBUG in verific.cc 2019-08-17 14:49:55 +02:00
verilog substr() -> compare() 2019-08-07 12:20:08 -07:00