yosys/backends
Robin Ole Heinemann 0f762f75a6 cxxrtl: fix vcd writer scope handling
The vcd writer incorrectly treated two scope vectors as the same, whenever
they have the same length of entries and the last item matches.
This is however not always true, for example consider a current_scope of
["top", "something0", "same"]
and a scope of
["top", "something1", "same"]
2024-10-12 14:41:53 +01:00
..
aiger write_xaiger: Get by without endianness helpers 2024-09-03 08:59:09 +02:00
aiger2 aiger2: Try to fix VS build 2024-10-07 12:27:37 +02:00
blif Ignore $scopeinfo in write_blif 2024-02-06 17:51:29 +01:00
btor tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
cxxrtl cxxrtl: fix vcd writer scope handling 2024-10-12 14:41:53 +01:00
edif Ignore $scopeinfo in write_edif 2024-02-06 17:51:29 +01:00
firrtl Ignore $scopeinfo in write_firrtl 2024-02-06 17:51:29 +01:00
functional Add TODO for missing help messages 2024-10-08 08:47:51 +02:00
intersynth Intersynth URL 2021-06-09 12:42:52 +02:00
jny chore: fix master branch refs 2024-03-24 00:41:54 -04:00
json Ignore $scopeinfo in write_json 2024-02-06 17:51:29 +01:00
rtlil dump: Update help after option removal 2024-09-17 10:46:20 +02:00
simplec tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
smt2 smtbmc: escape path identifiers 2024-09-24 03:01:49 +01:00
smv Ignore $scopeinfo in write_smv 2024-02-06 17:51:29 +01:00
spice Ignore $scopeinfo in write_spice 2024-02-06 17:51:29 +01:00
table Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
verilog write_verilog: don't `assign` to a `reg`. 2024-04-03 13:06:45 +02:00