yosys/passes
Eddie Hung 5c277c6325 Fix and test for balanced case 2019-06-06 14:21:34 -07:00
..
cmds Major rewrite of wire selection in setundef -init 2019-06-05 10:26:48 +02:00
equiv Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Refactor hierarchy wand/wor handling 2019-05-28 16:43:25 +02:00
memory memory_bram: Fix multiport make_transp 2019-04-07 16:56:31 +01:00
opt Fix and test for balanced case 2019-06-06 14:21:34 -07:00
pmgen Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 2019-05-28 17:17:56 +02:00
proc Improve proc full_case detection and handling, fixes #931 2019-04-18 15:13:47 +02:00
sat Error out if no top module given before 'sim' 2019-06-05 14:16:24 -07:00
techmap Move muxpack from passes/techmap to passes/opt 2019-06-06 12:15:13 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00