Jannis Harder d8cdc213a6 rename -witness: Bug fix and rename formal cells ... Rename formal cells in addition to witness signals. This is required to reliably track individual property states for the non-smtbmc flows. Also removes a misplced `break` which resulted in only partial witness renaming.		2024-03-04 16:53:03 +01:00
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cmds	rename -witness: Bug fix and rename formal cells	2024-03-04 16:53:03 +01:00
equiv	equiv_simple: Fix seed handling in non-short mode	2023-10-03 13:05:42 +02:00
fsm	add option to fsm_detect to ignore self-resetting	2023-01-30 16:12:53 +01:00
hierarchy	hierarchy: Without a known top module, derive all deferred modules	2024-02-06 10:31:40 +01:00
memory	Fix printf formats	2024-01-15 12:07:54 +01:00
opt	Merge pull request #4084 from jix/scopeinfo	2024-02-12 09:51:22 +01:00
pmgen	Address `SigBit`/`SigSpec` confusion issues under c++20	2024-02-08 17:48:36 +01:00
proc	Merge pull request #4218 from kivikakk/proc_rom-actionless-switch	2024-02-19 16:21:40 +01:00
sat	clk2fflogic: Fix handling of $check cells	2024-02-14 11:42:27 +01:00
techmap	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00
tests	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00