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yosys/passes
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Martin Povišer 1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate 
peepopt: Add formal opt to rewrite latches to ffs in clock gates
 		2024-11-11 14:49:09 +01:00
..
cmds Merge pull request #4707 from povik/stat-unused 2024-11-05 09:38:29 +01:00
equiv equiv_simple: Take FFs into account for driver map 2024-02-21 12:05:52 +01:00
fsm rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
hierarchy rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
memory rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
opt rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
pmgen Merge pull request #4525 from georgerennie/peepopt_clock_gate 2024-11-11 14:49:09 +01:00
proc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
sat Merge pull request #4525 from georgerennie/peepopt_clock_gate 2024-11-11 14:49:09 +01:00
techmap bufnorm: preserve constant bits driving wires 2024-11-07 11:48:48 +01:00
tests rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00