mirror of https://github.com/YosysHQ/yosys.git
114 lines
2.8 KiB
Verilog
114 lines
2.8 KiB
Verilog
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module TB_GND(ok);
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wire MY_G, XL_G;
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MY_GND MY(.G(MY_G));
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XL_GND XL(.G(XL_G));
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output ok = MY_G == XL_G;
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endmodule
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module TB_INV(ok, I);
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input I;
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wire MY_O, XL_O;
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MY_INV MY(.O(MY_O), .I(I));
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XL_INV XL(.O(XL_O), .I(I));
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output ok = MY_O == XL_O;
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endmodule
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module TB_LUT1(ok, I0);
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input I0;
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wire [1:0] MY_O, XL_O;
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genvar i;
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generate for (i=0; i<2; i=i+1) begin:V
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MY_LUT1 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0));
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XL_LUT1 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0));
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end endgenerate
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output ok = MY_O == XL_O;
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endmodule
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module TB_LUT2(ok, I0, I1);
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input I0, I1;
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wire [3:0] MY_O, XL_O;
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genvar i;
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generate for (i=0; i<4; i=i+1) begin:V
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MY_LUT2 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1));
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XL_LUT2 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1));
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end endgenerate
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output ok = MY_O == XL_O;
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endmodule
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module TB_LUT3(ok, I0, I1, I2);
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input I0, I1, I2;
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wire [7:0] MY_O, XL_O;
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genvar i;
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generate for (i=0; i<8; i=i+1) begin:V
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MY_LUT3 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2));
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XL_LUT3 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2));
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end endgenerate
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output ok = MY_O == XL_O;
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endmodule
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module TB_LUT4(ok, I0, I1, I2, I3);
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input I0, I1, I2, I3;
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wire [15:0] MY_O, XL_O;
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genvar i;
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generate for (i=0; i<16; i=i+1) begin:V
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MY_LUT4 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
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XL_LUT4 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
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end endgenerate
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output ok = MY_O == XL_O;
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endmodule
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module TB_LUT5(ok, I0, I1, I2, I3, I4);
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input I0, I1, I2, I3, I4;
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wire [31:0] MY_O, XL_O;
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genvar i;
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generate for (i=0; i<32; i=i+1) begin:V
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MY_LUT5 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4));
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XL_LUT5 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4));
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end endgenerate
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output ok = MY_O == XL_O;
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endmodule
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module TB_LUT6(ok, I0, I1, I2, I3, I4, I5);
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input I0, I1, I2, I3, I4, I5;
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wire [63:0] MY_O, XL_O;
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genvar i;
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generate for (i=0; i<64; i=i+1) begin:V
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MY_LUT6 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5));
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XL_LUT6 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5));
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end endgenerate
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output ok = MY_O == XL_O;
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endmodule
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module TB_MUXCY(ok, CI, DI, S);
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input CI, DI, S;
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wire MY_O, XL_O;
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MY_MUXCY MY(.O(MY_O), .CI(CI), .DI(DI), .S(S));
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XL_MUXCY XL(.O(XL_O), .CI(CI), .DI(DI), .S(S));
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output ok = MY_O == XL_O;
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endmodule
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module TB_MUXF7(ok, I0, I1, S);
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input I0, I1, S;
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wire MY_O, XL_O;
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MY_MUXF7 MY(.O(MY_O), .I0(I0), .I1(I1), .S(S));
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XL_MUXF7 XL(.O(XL_O), .I0(I0), .I1(I1), .S(S));
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output ok = MY_O == XL_O;
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endmodule
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module TB_VCC(ok);
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wire MY_P, XL_P;
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MY_VCC MY(.P(MY_P));
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XL_VCC XL(.P(XL_P));
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output ok = MY_P == XL_P;
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endmodule
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module TB_XORCY(ok, CI, LI);
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input CI, LI;
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wire MY_O, XL_O;
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MY_XORCY MY(.O(MY_O), .CI(CI), .LI(LI));
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XL_XORCY XL(.O(XL_O), .CI(CI), .LI(LI));
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output ok = MY_O == XL_O;
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endmodule
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