mirror of https://github.com/YosysHQ/yosys.git
121 lines
2.0 KiB
Verilog
121 lines
2.0 KiB
Verilog
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module IBUF(O, I);
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output O;
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input I;
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assign O = I;
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endmodule
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module OBUF(O, I);
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output O;
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input I;
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assign O = I;
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endmodule
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module GND(G);
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output G;
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assign G = 0;
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endmodule
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module INV(O, I);
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input I;
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output O;
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assign O = !I;
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endmodule
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module LUT1(O, I0);
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parameter INIT = 0;
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input I0;
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wire [1:0] lutdata = INIT;
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wire [0:0] idx = { I0 };
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output O;
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assign O = lutdata[idx];
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endmodule
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module LUT2(O, I0, I1);
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parameter INIT = 0;
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input I0, I1;
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wire [3:0] lutdata = INIT;
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wire [1:0] idx = { I1, I0 };
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output O;
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assign O = lutdata[idx];
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endmodule
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module LUT3(O, I0, I1, I2);
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parameter INIT = 0;
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input I0, I1, I2;
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wire [7:0] lutdata = INIT;
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wire [2:0] idx = { I2, I1, I0 };
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output O;
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assign O = lutdata[idx];
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endmodule
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module LUT4(O, I0, I1, I2, I3);
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parameter INIT = 0;
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input I0, I1, I2, I3;
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wire [15:0] lutdata = INIT;
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wire [3:0] idx = { I3, I2, I1, I0 };
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output O;
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assign O = lutdata[idx];
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endmodule
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module LUT5(O, I0, I1, I2, I3, I4);
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parameter INIT = 0;
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input I0, I1, I2, I3, I4;
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wire [31:0] lutdata = INIT;
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wire [4:0] idx = { I4, I3, I2, I1, I0 };
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output O;
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assign O = lutdata[idx];
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endmodule
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module LUT6(O, I0, I1, I2, I3, I4, I5);
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parameter INIT = 0;
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input I0, I1, I2, I3, I4, I5;
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wire [63:0] lutdata = INIT;
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wire [5:0] idx = { I5, I4, I3, I2, I1, I0 };
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output O;
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assign O = lutdata[idx];
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endmodule
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module MUXCY(O, CI, DI, S);
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input CI, DI, S;
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output O;
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assign O = S ? CI : DI;
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endmodule
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module MUXF7(O, I0, I1, S);
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input I0, I1, S;
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output O;
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assign O = S ? I1 : I0;
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endmodule
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module MUXF8(O, I0, I1, S);
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input I0, I1, S;
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output O;
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assign O = S ? I1 : I0;
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endmodule
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module VCC(P);
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output P;
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assign P = 1;
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endmodule
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module XORCY(O, CI, LI);
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input CI, LI;
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output O;
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assign O = CI ^ LI;
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endmodule
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module CARRY4(CO, O, CI, CYINIT, DI, S);
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output [3:0] CO, O;
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input CI, CYINIT;
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input [3:0] DI, S;
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wire ci_or_cyinit;
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assign O = S ^ {CO[2:0], ci_or_cyinit};
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assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
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assign CO[1] = S[1] ? CO[0] : DI[1];
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assign CO[2] = S[2] ? CO[1] : DI[2];
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assign CO[3] = S[3] ? CO[2] : DI[3];
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assign ci_or_cyinit = CI | CYINIT;
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endmodule
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