yosys/passes
whitequark c5c57e3f5e flatten: rewrite memid in memwr actions. 2021-04-09 09:46:53 +00:00
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cmds Clarify bugpoint documentation regarding output 2021-03-24 16:24:33 -05:00
equiv equiv: Suggest running async2sync or clk2fflogic where appropriate. 2021-03-30 18:20:21 +02:00
fsm Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
hierarchy Sign extend port connections where necessary 2020-12-18 20:33:14 -07:00
memory memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
opt opt_clean: Remove init attribute bits together with removed DFFs. 2021-03-15 17:16:53 +01:00
pmgen Add _pm.h files to GENLIST, fixes vcxsrc target 2021-03-11 15:56:32 +01:00
proc proc_arst: Add special-casing of clock signal in conditionals. 2021-03-15 17:17:29 +01:00
sat sim: Avoid a crash on empty cell connection. 2021-03-08 17:03:31 +01:00
techmap flatten: rewrite memid in memwr actions. 2021-04-09 09:46:53 +00:00
tests Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00