yosys/tests/various/dynamic_part_select/latch_1990.v

13 lines
252 B
Verilog

module latch_1990 #(
parameter BUG = 1
) (
(* nowrshmsk = !BUG *)
output reg [1:0] x
);
wire z = 0;
integer i;
always @*
for (i = 0; i < 2; i=i+1)
x[z^i] = z^i;
endmodule