mirror of https://github.com/YosysHQ/yosys.git
13 lines
252 B
Verilog
13 lines
252 B
Verilog
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module latch_1990 #(
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parameter BUG = 1
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) (
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(* nowrshmsk = !BUG *)
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output reg [1:0] x
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);
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wire z = 0;
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integer i;
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always @*
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for (i = 0; i < 2; i=i+1)
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x[z^i] = z^i;
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endmodule
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