yosys/passes
Marcelina Kościelnicka 0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
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cmds Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
memory FfData: some refactoring. 2021-10-07 04:24:06 +02:00
opt FfData: some refactoring. 2021-10-07 04:24:06 +02:00
pmgen Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc proc_prune: Make assign removal and promotion per-bit, remember promoted bits. 2021-08-14 15:26:11 +02:00
sat FfData: some refactoring. 2021-10-07 04:24:06 +02:00
techmap dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
tests Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00